Output Buffer Circuit With Parallel Unit Drivers

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Solution Overview

Problem

In semiconductor devices like DRAM, the high current density through miniaturized wiring patterns leads to a migration phenomenon, risking disconnection due to shape changes, especially in the output buffer configurations.

Innovation Solution

The semiconductor device's I/O circuit is designed with a configuration of parallel-connected unit drivers in the pull-up and pull-down circuits, where the number of activated transistors can be adjusted by varying the enable signal distribution, allowing for controlled current flow and reduced wiring widths to prevent migration-induced disconnection, while maintaining sufficient cross-sectional area.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Volume of moving object

If the cross-sectional area of the wiring pattern is reduced due to miniaturization, then the device size is reduced, but the current density increases causing migration phenomenon and disconnection risk

Engineering Contradiction:
Improvedevice sizeVSAvoidwiring connection reliability
Core Design Contradiction:
Volume of moving objectVSReliability

Solution Approach 1:

The output buffer circuit is divided into multiple unit drivers (first unit driver, second unit driver, etc.) that can be independently controlled. By segmenting the current path through multiple parallel transistor channels, the current density on any single wiring pattern is reduced, preventing migration phenomenon while maintaining miniaturization benefits

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Multiple unit drivers are combined in parallel configuration to share the total output current. The first unit driver and second unit driver operate simultaneously to distribute current across multiple wiring patterns, reducing the current density on each individual wiring pattern and preventing disconnection

Inventive Principle:
Principle #5Merging (Combining)

2Power

If the number of activated transistors is increased to handle high current, then the current driving capability is improved, but the occupied area increases

Engineering Contradiction:
Improvecurrent driving capabilityVSAvoidoccupied area
Core Design Contradiction:
PowerVSArea of stationary object

Solution Approach 1:

The circuit employs dynamic control of unit drivers through enable signals that can activate or deactivate specific unit drivers based on current requirements. This dynamic switching allows the circuit to adjust its current driving capability on-demand, maintaining high power when needed while minimizing occupied area by only activating necessary transistor channels

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

Different unit drivers can be selectively activated based on local current requirements. The enable signal distribution is configured to activate only the necessary number of unit drivers for the given operating condition, optimizing the balance between current driving capability and occupied area by applying different activation patterns to different parts of the circuit

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS11705188B2Output buffer circuit with metal option
Publication Date: 2023.07.18 MICRON TECHNOLOGY INC
  • US11705188B2 patent drawing
  • US11705188B2 patent drawing
  • US11705188B2 patent drawing

AI summary

Disclosed herein is an apparatus that includes: first and second wiring patterns extending in a first direction, first and second transistors arranged adjacent to each other, and third to sixth wiring patterns extending in a second direction. The third wiring pattern is connected between the first wiring pattern and one of source/drain regions of the first transistor, the fourth wiring pattern is connected between the second wiring pattern and other of source/drain regions of the first transistor, the fifth wiring pattern is connected to one of source/drain regions of the second transistor, the fifth wiring pattern overlapping with the first wiring pattern, the sixth wiring pattern is connected to other of source/drain regions of the second transistor, the sixth wiring pattern overlapping with the second wiring pattern. The third and fourth wiring patterns are greater in width in the first direction than the fifth and sixth wiring patterns.