Dynamic NAND Sensing Circuit for Faster SRAM Read Access
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Solution Overview
Problem
Conventional SRAMs have long read access times due to the number of stages required to retrieve and latch stored data, limiting their efficiency in data storage operations.
Innovation Solution
A dynamic NAND sensing circuit is employed in SRAMs, where the ground voltage is supplied during read operations to enhance data retrieval, and the ground terminal floats during write or standby operations, reducing the number of stages involved in data sensing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional SRAM read operations use multiple stages to retrieve and latch data, then data reliability is ensured, but read access time increases
Solution Approach 1:
The patent extracts the ground supply connection from the sensing circuit during write and standby operations, causing the ground terminal to float. This isolation prevents ground potential interference during non-read operations while maintaining reliable data sensing during read operations, thereby reducing access time without compromising data reliability
Solution Approach 2:
The patent implements dynamic control of the ground terminal by using control signals to selectively connect or disconnect the ground supply during different operational phases. The ground terminal transitions from a fixed connection to a floating state based on operational mode, enabling faster read access while maintaining reliability when needed
2Stability of the object's composition
If the ground terminal is continuously connected to supply ground potential, then circuit stability is maintained, but sensing speed during read operations decreases
Solution Approach 1:
The patent applies periodic control signals to dynamically switch the ground terminal connection state. During read operations, the ground terminal is disconnected (floating) to enable fast sensing, while during write and standby operations, it is connected to maintain circuit stability. This periodic switching optimizes both speed and stability based on operational requirements
Data Source
AI summary
A circuit includes a first PMOS having a source coupled to a supply voltage and a gate coupled to a first bitline of a first memory cell; a second PMOS having a source coupled to the supply voltage and a gate coupled to a second bitline of a second memory cell; a first NMOS having a drain coupled to drains of the first and second PMOS transistors and a gate coupled to the first bitline; a second NMOS having a drain coupled to a source of the first NMOS and a gate coupled to the second bitline; a third PMOS precharging the first bitline to the supply voltage in response to a first precharge signal; and a fourth PMOS precharging the second bitline to the supply voltage in response to a second precharge signal. In response to the first and second precharge signals, the ground terminal is caused to float.