Vertical Resistive Memory Stack for Lower Bias and Cell Interference
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Solution Overview
Problem
Existing resistive memory devices face challenges in reducing channel domination force and effective channel length, leading to increased bias requirements for program-erase operations and inter-cell interference.
Innovation Solution
A resistive memory device with a stack structure featuring alternately stacked interlayer insulating and conductive layers, a vertical hole with concave or semicircular sidewalls, and a gate insulating layer, channel layer, and variable resistance layer formed along these sidewalls, which reduces channel domination force and effective channel length.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If the channel length is reduced to improve device scaling, then the bias required for program-erase operations increases
Solution Approach 1:
The patent transitions from a planar channel structure to a three-dimensional vertical channel structure by forming the channel layer along the sidewalls of the hole. This dimensional change allows the channel to extend vertically through the stack structure, effectively increasing the channel length in the vertical dimension while maintaining a compact footprint, thereby reducing the bias requirement for program-erase operations
2Quantity of substance
If variable resistance layers are placed closer together to increase storage density, then inter-cell interference increases
Solution Approach 1:
The patent introduces an insulating layer between adjacent variable resistance layers formed on opposite sidewalls of the hole. This intermediary insulating layer acts as a barrier that prevents electrical interaction and interference between neighboring memory cells, allowing higher storage density without increasing inter-cell interference
Data Source
AI summary
There are provided a resistive memory device and a manufacturing method of the resistive memory device. The resistive memory device includes: a stack structure in which a plurality of interlayer insulating layers and a plurality of conductive layers are alternately stacked; a hole penetrating the stack structure in a vertical direction; and a gate insulating layer, a channel layer, and a variable resistance layer, formed along sidewalls of the plurality of conductive layers, which are adjacent to the hole, and sidewalls of the plurality of interlayer insulating layers, which are adjacent to the hole.