Semiconductor X-Row Controller Power-Speed Tradeoff
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Solution Overview
Problem
Conventional semiconductor memory integrated circuits consume unnecessary power due to the internal circuit of non-selected banks being activated during high-speed operations, as the X address signal is stored and output to the predecoder regardless of the bank active signal.
Innovation Solution
The semiconductor memory integrated circuit incorporates an X-row controller with a high-speed-operation control circuit and a low-current-operation control circuit, allowing for switching between high-speed and low power consumption operations by controlling the latch circuit based on bank active signals, using input and output switching circuits to select between these circuits based on a switching signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the latch circuit stores and outputs the X address signal regardless of the bank active signal, then high-speed operation is achieved, but power consumption increases due to unnecessary activation of predecoder internal circuits in non-selected banks
Solution Approach 1:
The patent applies dynamics by making the system switchable between two operational modes: a high-speed mode where the latch circuit operates independently of the bank active signal, and a low-power mode where the latch circuit is controlled by the bank active signal. This dynamic switching allows the system to adapt its behavior based on operational requirements, resolving the contradiction between speed and power consumption.
Solution Approach 2:
The patent changes the control parameter of the latch circuit from always-active to conditionally-active based on the bank active signal. By modifying the operational state of the latch circuit (from unconditional storage/output to conditional storage/output), the system can reduce power consumption in non-selected banks while maintaining high-speed operation when needed.
2Use of energy by moving object
If the latch circuit is controlled by the bank active signal to reduce power consumption, then predecoder circuits in non-selected banks are deactivated, but operation speed decreases
Solution Approach 1:
The patent provides dynamic control over the latch circuit's operation mode. The system can switch between being controlled by the bank active signal (for low-power operation) and operating independently (for high-speed operation). This dynamic capability allows optimization of either power consumption or speed depending on the operational context.
Solution Approach 2:
The latch circuit is designed to serve multiple functions: it can operate in a power-saving mode when controlled by the bank active signal, or in a high-speed mode when operating independently. This multi-functionality allows the same circuit to address both power consumption concerns and speed requirements under different operating conditions.
3Adaptability or versatility
If multiple control circuits are integrated on a single chip to enable switching between high-speed and low-power operations, then versatility is improved, but device complexity increases
Solution Approach 1:
The patent merges multiple control circuits (high-speed operation control circuit and low-power operation control circuit) onto a single chip. By integrating these circuits and sharing common resources such as the latch circuit and predecoder, the system achieves versatility while minimizing the increase in overall device complexity compared to separate implementations.
Solution Approach 2:
The control circuits are designed with multi-functionality, where the same physical circuits can serve different operational modes. The high-speed control circuit and low-power control circuit share common infrastructure, allowing the system to provide multiple operational capabilities without proportionally increasing device complexity.
Data Source
AI summary
A semiconductor memory integrated circuit having an X-row controller which includes a high-speed-operation control circuit by which when receiving a bank active signal, a period for stopping a latch circuit from receiving the X address is produced after a predetermined time has elapsed, and in the other periods, the latch circuit receives and holds the X address; a low-current-operation control circuit by which when receiving no bank active signal, the latch circuit stops receiving the X address, and when receiving the bank active signal, the latch circuit holds the X address after a predetermined time has elapsed; a circuit for selecting whether the bank active signal is output to the high-speed-operation control circuit or the low-current-operation control circuit; and a circuit for selecting whether the latch-circuit control signal from the high-speed-operation control circuit or the latch-circuit control signal from the low-current-operation control circuit is output to the latch circuit.