3D DRAM Refresh Control Using Local Temperature Sensors
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Solution Overview
Problem
Thermal generation from system-on-chip (SoC) logic devices creates localized thermal regions (hotspots) that complicate dynamic random-access memory (DRAM) cell retention time control, potentially leading to failure in three-dimensional (3D) DRAM stacking configurations.
Innovation Solution
Implementing additional temperature sensors in selected regions of DRAM dies within a 3D DRAM stack, aligned with localized thermal regions of the SoC base die, to adjust refresh period control dynamically based on monitored temperature sensor values.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If 3D DRAM stacking is implemented above SoC base die, then memory capacity and bandwidth are improved, but localized thermal regions from SoC logic device negatively impact DRAM retention time
Solution Approach 1:
The patent segments the DRAM die into multiple regions, each with its own temperature sensor and refresh control. This allows independent temperature monitoring and refresh period adjustment for different regions, addressing the thermal impact on retention time while maintaining overall memory capacity.
Solution Approach 2:
The patent implements local temperature monitoring and refresh control for different regions of the DRAM die. Each region can have customized refresh periods based on its local temperature conditions, ensuring reliable retention time even in hot regions while maintaining high memory capacity overall.
2Measurement precision
If additional temperature sensors are added to monitor localized thermal regions, then thermal condition monitoring precision is improved, but device complexity increases
Solution Approach 1:
The patent divides the DRAM die into multiple regions with individual temperature sensors, enabling precise thermal monitoring of localized areas without requiring a complete temperature monitoring system across the entire device, thus balancing precision with manageable complexity.
Solution Approach 2:
The temperature sensors are integrated directly into the DRAM die structure, allowing the memory device to self-monitor its thermal conditions without requiring external monitoring equipment, thereby improving measurement precision while minimizing additional device complexity.
3Reliability
If refresh period control is adjusted dynamically based on temperature sensor values, then DRAM cell retention reliability is improved, but control system complexity increases
Solution Approach 1:
The patent implements region-specific refresh control where each DRAM region can have its own refresh period adjusted according to local temperature conditions. This localized approach improves retention reliability in hot regions while keeping the control system complexity manageable by only adjusting refresh parameters rather than redesigning the entire control architecture.
Solution Approach 2:
The patent dynamically adjusts the refresh period parameter based on temperature sensor readings. By changing only the refresh timing parameter rather than the fundamental refresh mechanism, the system improves retention reliability while minimizing increases in control system complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Ensures predetermined DRAM cell retention times by accommodating varying thermal conditions, reducing the risk of DRAM failure due to hotspot-induced thermal impacts.
Implementation Method 1
identifying one or more temperature sensors placed in selected regions of one or more memory dies
Implementation Method 2
Thermal generation from an SoC logic device complicates cell retention time control
Data Source
AI summary
A method for flexible memory refresh period control is described. The method includes identifying one or more temperature sensors placed in selected regions of one or more memory dies supported by a system-on-chip (SoC) base die during formation of a memory die stack. The method also includes monitoring temperature sensor values of the one or more temperature sensors during operation of the memory die stack. The method further includes adjusting a memory refresh period control of a region of a memory die from the one or more memory dies when a temperature sensor value of a temperature sensor corresponding to the region is greater than the temperature sensor values based on the monitoring.