3D Stacked Memory Signal Rerouting for Defective Via Paths
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Solution Overview
Problem
The high manufacturing costs and potential flaws in 3D stacked memory devices, particularly due to defects in conductive vias and memory cell arrays, hinder efficient signal transmission and device yield.
Innovation Solution
A memory device with a stacked structure incorporating conductive vias, memory chips, and a memory controller, equipped with a chip identification device and signal path switch, allows for detecting and rerouting signals through functional vias using reference values to manage and adjust signal transmission, thereby reducing manufacturing defects and costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If 3D stacked memory structure is used to increase integration, then storage capacity is improved, but manufacturing cost increases and defects in conductive vias occur
Solution Approach 1:
The patent implements preliminary detection of conductive via defects during the manufacturing process using test signals and detection circuits. By identifying defective vias before final assembly, the system can pre-configure alternative routing paths, preventing signal transmission failures and reducing post-manufacturing failures.
Solution Approach 2:
The patent changes the operational parameters of the memory device by dynamically selecting different conductive via paths based on detected defects. The system modifies signal routing parameters to bypass defective vias while maintaining functional performance, thus resolving the reliability issue without sacrificing storage capacity.
2Reliability
If redundant conductive vias are added to compensate for defects, then reliability is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent segments the conductive via routing into multiple independent paths, each capable of being individually activated or deactivated. This segmentation allows the system to isolate defective vias and route signals through alternative paths without requiring complete redundant routing structures, thereby reducing overall device complexity while maintaining reliability.
Solution Approach 2:
The patent implements dynamic routing selection where the system can adaptively choose optimal signal paths based on real-time detection of via defects. This dynamic approach eliminates the need for static redundant routing for all possible defect scenarios, reducing structural complexity while ensuring reliable signal transmission.
3Reliability
If additional metal line routings are implemented to bypass defective vias, then signal transmission is maintained, but manufacturing precision requirements and cost increase
Solution Approach 1:
The patent performs preliminary detection and mapping of conductive via defects during manufacturing, allowing the system to pre-configure alternative routing paths through software or configuration memory rather than requiring precise physical metal line modifications. This approach maintains signal transmission while significantly reducing manufacturing precision requirements.
Solution Approach 2:
The patent creates a logical copy or map of the conductive via network that includes defect information and alternative routing paths. This virtual routing model allows the system to bypass defective vias through configuration changes rather than physical metal line modifications, reducing manufacturing precision demands.
Data Source
AI summary
A memory device includes a stacked memory, a plurality of conductive vias, and a memory controller. The stacked memory includes a plurality of memory chips. Each memory chip includes at least one memory cell array, a chip identification device, and a signal path switch. The chip identification device is coupled to the at least one memory cell array. The signal path switch is coupled to the chip identification device. The conductive vias penetrate through the stacked memory. The memory controller is coupled to the stacked memory.