MRAM Write Current Feedback Circuit for Leakage Compensation
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Solution Overview
Problem
Existing memory devices using magnetoresistive random access memory (MRAM) face inefficiencies in write operations due to variations in current distribution and leakage currents, affecting data storage reliability and speed.
Innovation Solution
A memory device design that includes a first memory cell, a second memory cell, and a third circuit with interconnects, where the third circuit supplies a sum of currents to the interconnects, optimizing current distribution and minimizing leakage currents through feedback mechanisms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional current supply method is used in MRAM write operations, then write operation speed is maintained, but current distribution varies and leakage currents increase affecting reliability
Solution Approach 1:
The patent implements a feedback mechanism where the actual current flowing through the selected memory cell is sensed and compared with the target write current. Based on this comparison, the current supply is dynamically adjusted to compensate for leakage currents and ensure accurate write operations, thereby improving reliability without sacrificing write speed.
2Reliability
If higher current is supplied to compensate for leakage, then write operation reliability improves, but energy consumption increases
Solution Approach 1:
The feedback control mechanism precisely regulates the current supplied to memory cells by sensing actual current flow and adjusting the supply accordingly. This eliminates the need to over-compensate for leakage currents, maintaining reliable write operations while minimizing energy consumption by supplying only the necessary current.
Solution Approach 2:
The patent dynamically adjusts current parameters based on detected leakage levels and operational conditions. By changing current magnitude and timing parameters adaptively rather than using fixed high current, the system achieves reliable writes with optimized energy consumption.
3Reliability
If current distribution is optimized for reliability, then data storage accuracy improves, but circuit complexity increases
Solution Approach 1:
The patent employs a feedback control circuit that senses current flow and adjusts supply accordingly. This relatively simple feedback mechanism achieves optimized current distribution and reliable writes without requiring complex circuit architectures, maintaining ease of implementation while improving reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances data storage reliability and write operation efficiency by stabilizing current flow and reducing leakage currents, thereby improving the overall performance of MRAM devices.
Implementation Method 1
a magnetoresistance effect element MTJ connected between the selected word line WL<m> and the selected bit line BL<n>
Data Source
AI summary
According to one embodiment, a memory device includes a first memory cell, a second memory cell, a first interconnect connected to the first memory cell and the second memory cell, a second interconnect connected to the second memory cell, and a third circuit. The third circuit includes a first circuit connectable to the first interconnect and the second interconnect and a second circuit connectable to the first interconnect and the second interconnect. During a write operation or a read operation for the first memory cell, the first circuit outputs a first current to be supplied to the first memory cell, the second circuit outputs a third current based on a second current which flows through the second interconnect, and the third circuit supplies a sum of the first current and the third current to the first interconnect.