Word Line Voltage Compensation for Adjacent Cell Disturbance
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Solution Overview
Problem
Undesired voltage disturbances occur between target and adjacent memory cells due to parasitic capacitors during sensing and programming operations in ferroelectric memory devices, leading to erroneous memory operations.
Innovation Solution
The row decoder applies compensatory voltages to adjacent word lines to counteract the undesired parasitic capacitance, using reference and compensatory voltages to reduce voltage disturbances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If sensing or programming operations are performed on targeted memory cells, then information access or storage is achieved, but voltage disturbances occur on untargeted adjacent memory cells due to parasitic capacitors
Solution Approach 1:
The patent applies preliminary anti-action by applying compensatory voltages to adjacent word lines before and during sensing/programming operations on targeted memory cells. This preemptive measure counteracts the voltage disturbances that would otherwise be induced on adjacent memory cells through parasitic capacitive coupling, preventing erroneous operations before they occur.
Solution Approach 2:
The patent changes voltage parameters by applying different compensatory voltage levels to adjacent word lines depending on the operation being performed. During sensing operations, a first compensatory voltage is applied, while during programming operations, a second compensatory voltage is applied. These voltage parameters are specifically selected to counteract the parasitic capacitance effects and maintain stable operation of adjacent memory cells.
2Object-affected harmful factors
If compensatory voltages are applied to adjacent word lines, then voltage disturbances are reduced, but device complexity increases due to additional voltage control requirements
Solution Approach 1:
The patent implements universality by designing the row decoder to perform multiple functions: it selectively activates specific word lines for sensing or programming operations while simultaneously applying appropriate compensatory voltages to adjacent word lines. This multi-functionality is achieved through a unified voltage control mechanism that handles both selection and compensation tasks, reducing the need for separate dedicated compensation circuits.
Solution Approach 2:
The patent applies self-service by enabling the row decoder to automatically generate and apply the appropriate compensatory voltages based on the operation being performed. The system self-regulates the voltage levels on adjacent word lines without requiring external intervention or complex additional control logic, as the same decoder circuitry that selects target cells also manages the compensation scheme.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the reliability and reduces error rates in memory operations by minimizing voltage disturbances between memory cells.
Implementation Method 1
undesired voltage disturbances between target and adjacent memory cells due to parasitic capacitors
Data Source
AI summary
A memory cell may include a capacitor and a switch. Accessing the memory cell in a memory array of a memory device may include applying a word line voltage to the switch to electrically couple the capacitor to a data line. However, if not compensated for, applying the word line voltage may induce undesired voltages on adjacent memory cells of the memory arrays. Systems and methods are described to reduce an effect of one or more parasitic capacitors causing the undesired voltage disturbance. For example, the memory array may provide compensatory voltages to adjacent word lines of a target word line to compensate for such undesired parasitic capacitors. Accordingly, an undesired voltage disturbance of the memory cells may be reduced.