Floating Sense Amplifier Comparator Without Input Capacitors
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Solution Overview
Problem
Existing sense amplifiers for phase-change memories rely on input capacitors, which limit reading speed and accuracy due to long discharge windows and power consumption, especially when operating in shifted voltage domains.
Innovation Solution
A sense amplifier circuit with a floating comparator and a sense amplifier core that eliminates input capacitors, utilizing a differential input pair and offset compensation to enhance reading speed and reduce power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If input capacitors are used in the sense amplifier, then the memory can operate in shifted voltage domains, but the reading speed is limited due to long discharge windows
Solution Approach 1:
The patent removes the input capacitors from the sense amplifier circuit, extracting the problematic component that limited reading speed. This is achieved by redesigning the comparator input stage to directly accept differential voltages without requiring capacitor-based voltage domain shifting, thereby eliminating the long discharge window issue while maintaining voltage domain adaptability through alternative circuit toplogy
2Adaptability or versatility
If input capacitors are used in the sense amplifier, then voltage domain shifting is enabled, but power consumption increases
Solution Approach 1:
The patent eliminates the power-consuming input capacitors and their associated charge/discharge operations. The redesigned comparator uses a direct differential input stage that achieves voltage domain adaptability through transistor-level design rather than capacitor-based voltage shifting, significantly reducing dynamic power consumption during read operations
3Adaptability or versatility
If input capacitors are used in the sense amplifier, then the circuit can handle shifted voltage domains, but reading accuracy is limited
Solution Approach 1:
By removing the input capacitors, the patent eliminates the sources of reading errors associated with capacitor leakage, charge sharing, and discharge window timing. The new direct-coupled differential comparator provides more accurate voltage comparison by avoiding the intermediate capacitor storage and transfer steps that introduced measurement uncertainties
Solution Approach 2:
The patent introduces a specially designed differential comparator circuit as an intermediary between the bit lines and the decision logic. This comparator directly compares the differential voltages from the bit lines without requiring capacitor-based voltage domain conversion, providing more accurate and faster reading while maintaining compatibility with shifted voltage domains
Data Source
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AI summary
In a sense amplifier circuit (40) for a memory device, first (304L) and second (304R) input terminals are coupled to first (302L) and second (302R) memory sensing nodes, respectively. A comparator circuit (42) has first (402L) and second (402R) input nodes as well as first (306L) and second (306R) output nodes configured to produce first (IL(t)) and second (IR(t)) output currents, respectively. A first input transistor (MPCL) has a conductive channel arranged between the first comparator input node and the first comparator output node, and a control terminal coupled to an internal biasing node (COMPINT). A second input transistor (MPCR) has a conductive channel arranged between the second comparator input node and the second comparator output node, and a control terminal coupled to the internal biasing node (COMPINT). The first and second comparator input nodes are selectively couplable to each other, in response to a compensation signal (SA_CONNECT_BL) being asserted, or to the first and second input terminals, respectively, in response to the compensation signal being de-asserted. The internal biasing node is selectively couplable to a comparator biasing node (BIASPCOMP) in response to a bias enable signal (SA_ENAB_BL) being asserted, or is floating in response to the bias enable signal being de-asserted. A sensing circuit (44, 46) is coupled to the comparator output nodes (306L, 306R) and produces a memory reading signal (SA_OUT) as a function of a difference between the first and second output currents.