SRAM Row Decoder Negative Bias Wordline Drive
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing SRAM technologies face challenges in achieving high read/write speed without increasing leakage currents or area consumption, and are not compatible with all technologies, limiting their performance in mobile devices where compactness and low power consumption are crucial.
Innovation Solution
The proposed SRAM architecture employs a row decoder circuitry with negative bias generation circuitry and CMOS inverters to generate a negative bias voltage, reducing the threshold voltage of transistors and enhancing word line signal transition speed, while maintaining low power consumption and compact design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If low threshold voltage (LVT) MOS transistors are used in the word line driver circuit, then read/write speed is improved, but leakage currents increase causing increased power consumption
Solution Approach 1:
The patent changes the voltage parameter by introducing a negative bias voltage to the source of the n-channel transistor in the word line driver circuit. This parameter change reduces the threshold voltage of the transistor, enabling faster read/write operations without using LVT MOS transistors that would increase leakage currents and power consumption.
2Speed
If the size of transistors in the word line driver is increased, then read/write speed is improved, but area consumption increases
Solution Approach 1:
Instead of increasing transistor size to improve speed, the patent applies a negative bias voltage to reduce the threshold voltage of the existing transistor. This allows the same transistor size to achieve faster switching speeds, thereby improving read/write performance without increasing area consumption.
3Speed
If forward body bias is applied to transistors in the word line driver, then read/write speed is improved, but leakage currents increase causing increased power consumption
Solution Approach 1:
The patent implements a voltage parameter change by applying negative bias to the source terminal of the n-channel transistor. This effectively reduces the threshold voltage and improves switching speed without the need for forward body bias, thereby avoiding the associated increase in leakage currents and power consumption.
4Speed
If repeaters (buffers) are inserted in the word line, then read/write speed is improved, but area consumption increases
Solution Approach 1:
The patent improves read/write speed by changing the voltage parameter through negative bias application to the word line driver transistor. This enhances the driving capability and switching speed of the existing circuit without adding repeaters or buffers, thereby avoiding additional area consumption.
Data Source
AI summary
A row decoder includes decoder logic generating an initial word line signal, and two inverters. The first inverter is formed by a first p-channel transistor having a source coupled to a supply voltage and a gate receiving the initial word line signal. The second inverter is formed by a first n-channel transistor having a drain coupled to a drain of the first p-channel transistor, a source coupled to a shared ground line, and a gate receiving the initial word line signal. An inverse word line signal is generated at the drain of the first n-channel transistor. A second inverter inverts the inverse word line signal to produce a word line signal. Negative bias generation circuitry generates a negative bias voltage on the shared ground line when the initial word line signal is logic high, and otherwise couples the shared ground line to ground.