Multi-port Memory Architecture for High-bandwidth Optical Switching
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Solution Overview
Problem
The increasing bandwidth of transponder switches in optical networks leads to increased design and layout complexity of switching circuitry, particularly in converting serial bit streams to parallel data and back, due to the need for complex multiplexing and demultiplexing processes.
Innovation Solution
A multi-port memory system is implemented using groups of simpler multi-port memories, with write and read ports that allow simultaneous writing and reading of data units across multiple ports, and multiplexers that selectively supply copies of data units from memories to output ports, reducing the complexity of serial-to-parallel and parallel-to-serial conversion processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the bandwidth of the transponder switch is increased, then the data transmission capacity is improved, but the design and layout complexity of the switching circuitry increases
Solution Approach 1:
The memory system is divided into multiple groups of memories, where each group contains multiple memory devices. This segmentation allows the write port to supply copies of data units to subsets of memories in parallel, and enables multiple read ports to simultaneously access different memory groups, thereby increasing data transmission capacity while maintaining manageable circuit complexity through modular organization
Solution Approach 2:
The patent implements a hierarchical memory structure where multiple copies of data units are stored across nested levels of memory groups. Each memory group contains multiple memory devices that store identical data copies, creating a nested organization that enables simultaneous read operations from multiple ports while simplifying the control logic through repeated patterns
2Productivity
If complex multiplexing and demultiplexing processes are used for serial-to-parallel conversion, then the bandwidth is improved, but the circuitry design complexity increases
Solution Approach 1:
The write port pre-processes incoming data units by creating multiple copies and distributing them to different memory groups before read operations are required. This preliminary action of duplicating and positioning data in advance eliminates the need for complex real-time multiplexing during read operations, as multiple read ports can simultaneously access pre-positioned data copies without conflict
Solution Approach 2:
The patent creates multiple copies of each data unit and stores them in different memory groups. This copying strategy allows any read port to access any data unit from any memory group without requiring complex routing or multiplexing, as the desired data is already replicated and available at multiple locations, thereby simplifying the access circuitry
Data Source
AI summary
A multi-port memory may be formed from a plurality of “simpler” memories. In one implementation, the memory includes a write port and a number of memories provided in groups, such that the write port supplies each of a plurality of copies of the data unit to a subset of the memories, each of the subset of memories being provided in a corresponding one of the groups, a number of the copies of the data unit being greater than two. Multiplexers may be implemented, each of which being associated with a corresponding one of the groups of the memories. One of the plurality of multiplexers may be configured to selectively supply one of the copies of the data unit from one of the memories. A read port may receive the one of the copies of the data unit from the one of the multiplexers and output the one of the copies of the data unit.