Scalable Floating Body SRAM Cell Design for Memory Compiler Flexibility
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Solution Overview
Problem
Existing semiconductor memory devices, particularly DRAM cells, face challenges in scalability and complexity when designing memory arrays, as they require complicated solutions to adjust memory cell sizes and maintain robustness and repeatability for compiler flexibility.
Innovation Solution
The development of a scalable floating body SRAM cell with multiple transistor configurations, including three-transistor and four-transistor designs, that allows for modular and repeatable memory cell design, enabling flexible memory array size adjustments and dual-port functionality through separate read and write bit lines, and a method for a memory compiler to select the appropriate SRAM cell type based on user input criteria.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If conventional DRAM cells are used, then data storage is achieved, but scalability and cell size reduction are limited due to capacitor requirements
Solution Approach 1:
The patent removes the capacitor component from the conventional 1T1C DRAM cell structure, extracting only the transistor element and utilizing the floating body effect to store charge. This extraction of the capacitor enables significantly smaller cell size while maintaining data storage functionality through the floating body's inherent charge storage capability.
Solution Approach 2:
The patent replaces the mechanical/electrical capacitor structure with a quantum mechanical floating body effect. The floating body region, isolated by depletion regions, stores charge through quantum confinement effects, substituting the traditional capacitor mechanism with a solid-state quantum effect that enables scaling.
2Quantity of substance
If memory cell size is reduced for scaling, then higher density is achieved, but robustness and repeatability for compiler flexibility are compromised
Solution Approach 1:
The patent segments the floating body memory cell into distinct functional regions: the floating body region for charge storage, source/drain regions for electrical contact, and gate regions for control. This segmentation allows each component to be optimized independently, maintaining robustness while enabling scaling and compiler flexibility through modular design.
Solution Approach 2:
The floating body cell structure serves multiple functions: charge storage, logic operation, and scalability. The same floating body region that stores charge also enables the cell to be configured in various transistor arrangements (1T, 2T, 3T, 4T cells), providing universality across different memory densities and compiler requirements.
3Adaptability or versatility
If multiple transistor configurations are implemented for compiler flexibility, then adaptability is improved, but device complexity increases
Solution Approach 1:
The floating body cell serves as a universal building block that can be configured in multiple transistor arrangements (1T, 2T, 3T, 4T cells) depending on the application requirements. The same basic floating body structure enables different memory array configurations, providing adaptability without requiring fundamentally different cell designs for each configuration type.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides a robust and scalable memory cell design that supports flexible memory array configurations, enabling efficient read and write operations while maintaining stability and reducing complexity in memory compiler implementations.
Implementation Method 1
a floating body memory cell comprising: a floating body region configured to be charged to a level indicative of a state of the memory cell
Data Source
AI summary
A floating body SRAM cell that is readily scalable for selection by a memory compiler for making memory arrays is provided. A method of selecting a floating body SRAM cell by a memory compiler for use in array design is provided.