Pseudo-Multiport Memory Word Line Drivers
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor memory devices face high power consumption when operated as multiport memory, particularly when transitioning between read and write operations, leading to increased electrical power usage.
Innovation Solution
A semiconductor memory device is designed with pseudo-multiport cells, an address decoder, a first word line driver, and a second word line driver with NOR logic to selectively activate word lines for reading and writing, optimizing power usage by activating both word lines only during writing and one word line during reading.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a multiport memory is operated as a single port memory with both word lines activated during read operations, then data retrieval capability is maintained, but power consumption increases
Solution Approach 1:
The patent applies dynamics by making the word line activation state changeable based on operation mode. Through the word line driver circuit with NOR logic, the system can dynamically adjust which word lines are activated during read operations - activating only the necessary word line for single port operation rather than both word lines, thereby reducing power consumption while maintaining operational flexibility
Solution Approach 2:
The patent changes the parameter of word line activation state based on operation mode. By using the NOR logic circuit in the word line driver, the system modifies the activation parameters of word lines according to whether read or write operations are performed, enabling single port operation mode where only one word line is activated during reads, thus reducing power consumption
2Reliability
If both word lines are activated during read operations in multiport memory, then read capability is ensured, but unnecessary power consumption occurs
Solution Approach 1:
The patent extracts the unnecessary word line activation by using the NOR logic circuit to selectively disable one of the two word lines during read operations. The word line driver circuit extracts and removes the redundant activation signal, ensuring that only the necessary word line is activated for reading data, thereby eliminating unnecessary power consumption while maintaining reliable read capability
Solution Approach 2:
The system applies dynamics by making word line activation adaptive to the operation type. The NOR logic-based word line driver dynamically adjusts which word lines are activated based on whether read or write operations are occurring, ensuring that during read operations only the necessary word line is activated, thus reducing unnecessary power consumption while maintaining read reliability
3Adaptability or versatility
If a multiport memory structure is used, then versatility is improved, but power consumption increases during transitions between operations
Solution Approach 1:
The patent applies segmentation by dividing the word line activation control into separate functional parts - a first word line driver for write operations and a second word line driver with NOR logic for read operations. This segmentation allows each driver to be optimized for its specific function, with the second driver being able to selectively activate only the necessary word line during reads, thereby reducing power consumption during operation transitions while maintaining multiport versatility
Solution Approach 2:
The patent makes the word line activation dynamic and adaptive to operation mode. The second word line driver with NOR logic dynamically adjusts word line activation based on whether read or write operations are occurring, enabling the multiport memory to transition efficiently between operations with reduced power consumption by only activating necessary word lines rather than maintaining all word lines in an active state
Data Source
AI summary
A semiconductor memory device includes an address decoder to decode an address specifying pseudo-multiport cells in memory blocks, a first word line driver to output a word line selection signal selecting one of word lines of one of the pseudo-multiport cells based on a row address in the address, and a second word line driver having an output part to output the word line selection signal into one of a pair of the word lines of the pseudo-multiport cell, and a NOR logic part to output NOR of the word line selection signal and a read/write selection signal into the other one of the pair of the word lines, the read/write selection signal selecting writing or reading operations. The second word line driver activates the pair of the word lines for writing data, and activates one of the pair of the word lines for reading data.


