Back Bias Voltage Supply for Memory Cell Arrays
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Solution Overview
Problem
Semiconductor devices face challenges in maintaining consistent current flow during write operations across memory cells, especially as distance from the write driver circuit increases, leading to potential failures in data recording due to insufficient current supply.
Innovation Solution
The implementation of a back bias voltage supply unit that provides different levels of back bias voltages to memory cells based on their distance from the write driver circuit, ensuring consistent current flow through the use of a negative voltage pumping section and trimming sections to adjust voltage levels, and the inclusion of resistance variable elements such as metal oxides or phase change substances with tunnel barrier layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are positioned farther from the write driver circuit to increase storage capacity, then the memory array can accommodate more cells, but the current supply to distant memory cells becomes insufficient leading to write operation failures
Solution Approach 1:
The cell array is divided into multiple regions (first region, second region, third region) based on their distance from the write driver circuit. Each region is assigned a different back bias voltage level, allowing independent optimization of current supply for each segment. This segmentation enables the system to maintain reliable write operations across all memory cells regardless of their position in the array.
Solution Approach 2:
Different back bias voltage levels are applied to different regions of the cell array according to their specific needs. Memory cells farther from the write driver circuit receive higher back bias voltages to compensate for current loss, while closer cells receive lower voltages. This local quality adjustment ensures optimal current supply to each memory cell based on its position, maintaining write reliability across the entire array.
2Device complexity
If uniform back bias voltage is applied to all memory cells, then the circuit design is simplified, but current flow becomes inconsistent across memory cells at different distances from the write driver circuit
Solution Approach 1:
The back bias voltage supply is segmented into multiple levels corresponding to different regions of the cell array. The back bias voltage supply unit provides at least two different back bias voltages (first back bias voltage and second back bias voltage) to different regions, ensuring that each region receives the appropriate voltage level for stable current flow while maintaining a relatively simple overall circuit structure.
3Reliability
If higher back bias voltage is supplied to distant memory cells to maintain current flow, then write operation reliability improves, but power consumption increases
Solution Approach 1:
Higher back bias voltages are applied only to memory cells that are farther from the write driver circuit and require additional current compensation. Memory cells closer to the write driver circuit receive lower back bias voltages, reducing unnecessary power consumption. This localized voltage adjustment maintains data recording stability for distant cells while minimizing overall power consumption of the memory device.
Data Source
AI summary
An electronic device including a semiconductor memory. The semiconductor memory includes a cell array divided into at least two regions each of which includes a plurality of memory cells each including a transistor and a resistance variable element; a write driver circuit configured to supply write current to a memory cell selected among memory cells in the cell array; and a back bias voltage supply unit configured to supply back bias voltages with different levels to the regions in the cell array.