Write Recovery Time Control Circuit for Semiconductor Memory
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Solution Overview
Problem
Conventional semiconductor memory devices face challenges in controlling write recovery time effectively, leading to improper operation due to premature disabling of the word line before data is fully written into memory cells.
Innovation Solution
A semiconductor memory device with a write recovery time control circuit that includes a clock buffer, command decoder, and write recovery time control circuit, utilizing a master and slave circuit configuration to gate bank pre-charge control signals in a wave pipeline mode, ensuring data is fully written before disabling the word line.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the word line is disabled by a pre-charge command before data is sufficiently written into the memory cell, then the operation speed can be increased, but data integrity deteriorates due to premature disabling
Solution Approach 1:
The patent applies preliminary action by generating the pre-charge command signal after a predetermined time period following the write command, ensuring data is sufficiently written before the word line is disabled. The time period generator creates this predetermined time delay, allowing the memory cell to complete data writing before the pre-charge command activates and disables the word line, thus preventing data integrity deterioration while maintaining high operation speed.
2Device complexity
If conventional circuits are used to control write recovery time, then the circuit structure is simple, but the number of flip-flops increases and signal skew occurs
Solution Approach 1:
The patent applies the extraction principle by removing unnecessary flip-flops from the conventional circuit structure. The time period generator uses a minimal number of flip-flops to generate the predetermined time delay, extracting only the essential timing control function while eliminating redundant flip-flops that would increase circuit complexity and cause signal skew in conventional designs.
Solution Approach 2:
The patent replaces the conventional mechanical counting approach using multiple flip-flops with a time period generator that uses a minimal number of flip-flops combined with delay circuits. This substitution reduces the number of flip-flops required while maintaining the same timing control functionality, thereby reducing signal skew and circuit complexity.
3Measurement precision
If more flip-flops are used to control write recovery time, then timing control precision is improved, but power consumption increases
Solution Approach 1:
The patent extracts only the essential timing control function using a minimal number of flip-flops in the time period generator, removing unnecessary flip-flops that would increase power consumption. This extraction approach maintains sufficient timing control precision for write recovery time while significantly reducing the power consumption associated with operating multiple flip-flops.
Data Source
AI summary
A semiconductor memory device may include a clock buffer, a command decoder and a write recovery time control circuit. The clock buffer may generate an internal clock signal based on an external clock signal. The command decoder may generate a write command signal by decoding an external command signal. The write recovery time control circuit may gate a plurality of bank pre-charge control signals in a wave pipeline mode based on the internal clock signal, the write command signal and a write recovery time control signal having a plurality of bits to generate a plurality of gated bank pre-charge control signals. Therefore, the semiconductor memory device may decrease a number of flip-flops required to control a write recovery time.