Bit Line Voltage Sweeping for DRAM Sense Amplifier Testing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In DRAM devices, it is difficult to check the functionality of a sense amplifier (SA) without using data from a memory cell, and determining offset voltages and sensing margins of the SA is challenging due to both bit lines being charged to the same voltage during standby mode.
Innovation Solution
A semiconductor device with a sensing circuit that includes separate charging circuits for the bit line and bit line bar, allowing for the application of different voltages to test SA functionality, determine offset voltages, and measure leakage currents without using data from memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate charging circuits are applied to BL and BLB to enable SA testing, then SA functionality can be tested without memory cell data, but device complexity increases
Solution Approach 1:
The sensing circuit is designed to perform multiple functions: normal data sensing during DRAM operation and standalone SA functionality testing. The charging circuits can operate in two modes: equalizing BL and BLB during normal operation, or applying different voltages during testing mode, allowing one circuit structure to serve dual purposes without requiring completely separate test equipment
Solution Approach 2:
Dummy capacitors are introduced as intermediary elements that simulate memory cell capacitor behavior during SA testing. These dummy capacitors allow the sensing circuit to be tested with controlled voltage sources without requiring actual memory cell data, bridging the gap between simple voltage application and realistic sensing conditions
2Productivity
If both BL and BLB are charged to the same voltage during standby mode, then the DRAM operates normally, but offset voltages and sensing margins cannot be determined
Solution Approach 1:
The charging circuits are designed to dynamically adjust their operation based on mode requirements. During normal DRAM operation, they equalize BL and BLB voltages for proper standby state. During testing mode, they can apply different voltages to BL and BLB to sweep through various conditions and determine offset voltages and sensing margins, allowing the system to adapt between operational states
3Reliability
If data from memory cells is used to test SA functionality, then the testing can be performed, but it cannot determine SA offset voltages independently of memory cell data
Solution Approach 1:
Dummy capacitors serve as intermediary test elements that replicate the electrical characteristics of memory cell capacitors without containing actual memory data. These dummy capacitors can be charged to specific voltages and connected to the sensing circuit, enabling independent SA characterization including offset voltage determination, while maintaining realistic sensing conditions
Data Source
AI summary
An integrated circuit includes a sense amplifier connected to a bit line and a bit line bar, a first memory cell configured to store a data signal and selectively output the data signal on at least one of the bit line and the bit line bar in response to a word line signal, a first circuit connected between a first voltage terminal configured to receive a first external voltage and the bit line and having a first enable terminal configured to receive a first enable signal, wherein the first external voltage is different than the data signal, and a second circuit connected between a second voltage terminal configured to receive a second external voltage and the bit line bar and having a second enable terminal configured to receive a second enable signal, wherein the second external voltage is different than the data signal and the first external voltage.