SRAM Peripheral Circuit With Reverse-Bias Sleep Leakage Reduction
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Solution Overview
Problem
Conventional semiconductor memory devices using p-type transistors for access transistors lack a detailed disclosure of their peripheral circuits, particularly for sleep processing, leading to inefficiencies and increased leak currents.
Innovation Solution
A peripheral circuit for SRAM cells using p-type transistors as access transistors is introduced, featuring a first switch circuit on the higher potential power supply side to reduce leak currents through a reverse bias effect, and a second switch circuit to facilitate power supply design in semiconductor integrated circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a p-type transistor is used for the access transistor in an SRAM cell, then the circuit configuration can be simplified and manufacturing can be easier, but leak currents increase and sleep processing becomes inefficient
Solution Approach 1:
The power supply connection is segmented into two parts: a first power supply connection for the access transistors and a second power supply connection for the drive transistors. This segmentation allows independent control of power supply voltages, enabling the access transistors to be turned off during sleep mode while maintaining proper biasing for the drive transistors, thereby reducing leak currents without compromising manufacturing simplicity
Solution Approach 2:
A switch element is introduced as an intermediary component between the power supply and the internal nodes of the SRAM cell. This switch element controls the connection to the first power supply, enabling selective powering of access transistors during sleep mode operation, thus reducing leak currents while preserving the benefits of p-type access transistor configuration
2Device complexity
If the first switch circuit is provided on the first power supply side, then the circuit design is simplified, but leak currents increase due to lack of reverse bias effect
Solution Approach 1:
Instead of placing the switch element on the conventional first power supply side, the invention inverts the approach by placing it on the second power supply side. This inversion enables the switch to control the power supply connection in a way that generates reverse bias effect across the transistors during sleep mode, effectively reducing leak currents while maintaining manageable device complexity
Solution Approach 2:
The invention changes the voltage parameter configuration by providing different power supply voltages to different transistor groups. The second power supply voltage is configured to create reverse bias conditions when the switch element is off, transforming the electrical parameters to achieve leak current reduction without significantly increasing device complexity
3Ease of operation
If conventional sleep processing is used without specific switch circuit control, then the circuit operation is simpler, but leak currents are not reduced efficiently
Solution Approach 1:
The switch element is configured to be turned off in advance before the SRAM cell enters sleep mode. This preliminary action disconnects the power supply from the access transistors before they would otherwise begin to leak current, enabling efficient leak current reduction while requiring minimal changes to the ease of operation of the overall circuit
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces leak currents and simplifies power supply design by leveraging the reverse bias effect, enhancing the efficiency and performance of the semiconductor memory device.
Implementation Method 1
leak currents can be more reduced due to a so-called reverse bias effect in the first and second p-type transistors (drive transistors) and the third and fourth p-type transistors (access transistors)
Data Source
AI summary
A semiconductor memory device includes memory cells and a write/read circuit. Each of the memory cells includes p-type drive transistors, n-type load transistors, and p-type access transistors connected to a bit line pair. A sense amplifier circuit includes p-type transistors and n-type transistors. The semiconductor memory device further includes: a first switch circuit including a first switch element and a second switch element; and a second switch circuit including a third switch element.