DDR SDRAM Data Strobe Signal Calibration via Impedance Adjustment
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Solution Overview
Problem
Conventional methods for calibrating synchronous dynamic random access memory (SDRAM) systems fail to minimize data errors due to crosstalk and impedance mismatches, which impair signal integrity and induce ring-back noise, even when using phase skew calibration techniques.
Innovation Solution
A method that adjusts the data signal driver circuit to impair impedance matching during system-level memory tests, performing tests at various phase skew values between the data strobe and data signals, and determining an optimal phase skew value based on the lowest error count to set the data strobe signal delay for the memory controller.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If conventional phase skew calibration is used to sample DQ signal at the center of the eye, then sampling timing is standardized, but data errors increase due to ring-back noise from impedance mismatches
Solution Approach 1:
The patent changes the sampling timing parameter from the conventional center-of-eye point to an optimized point that accounts for ring-back noise effects. By adjusting the phase skew value based on measured signal characteristics rather than assuming center-of-eye optimality, the system achieves lower error rates while maintaining operational simplicity.
2Reliability
If impedance matching is optimized in the data signal channel, then signal integrity improves, but calibration complexity increases due to need for sophisticated test procedures
Solution Approach 1:
The patent performs preliminary impedance mismatch characterization during manufacturing or initial setup by introducing deliberate mismatches and measuring their effects. This pre-characterization data is stored and used during normal operation to compensate for impedance issues without requiring complex real-time calibration procedures, thus achieving good signal integrity while keeping calibration simple.
3Reliability
If crosstalk effects are minimized through trace routing optimization, then signal integrity improves, but manufacturing complexity and cost increase
Solution Approach 1:
The patent converts the harmful crosstalk effect into a useful calibration reference. By deliberately introducing known crosstalk conditions or using existing crosstalk patterns as test signals, the system characterizes the interference effects and compensates for them through calibration. This approach achieves good signal integrity without requiring expensive manufacturing optimizations, as the crosstalk is managed through software/firmware calibration rather than hardware redesign.
Data Source
AI summary
In calibrating the phase skew between an SDRAM data strobe (“DQS”) signal and data (“DQ”) signal in a device, the data signal driver circuit impedance is adjusted to impair impedance matching on the DQ signal channel while system-level memory tests are performed. The phase skew is stepped through a range during the memory tests, and an error count is determined for each test. The memory tests may emulate mission-mode operation of the device. Following the memory tests, an optimal phase skew corresponding to a lowest error count is determined. The DQS signal may be delayed with respect to the DQ signals by a value corresponding to the optimal phase skew in subsequent mission-mode operation of the device.