Memory Device DQ Pin Operation Code Configuration
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As memory device technology advances and operating speeds increase, the time required to set mode registers in memory devices grows, especially when multiple devices are used, necessitating a reduction in the time needed to configure these settings.
Innovation Solution
The implementation of a memory device architecture that includes separate data input/output pins for receiving operation codes, allowing for independent and simultaneous configuration of mode registers across multiple memory devices, using a command pin and data strobe signal to efficiently set operation modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If memory devices support increasing number of functions and higher operating speeds, then capability and performance are improved, but time required to set mode registers increases
Solution Approach 1:
The patent divides the mode register setting process into multiple parallel channels by providing separate data input/output pins (first DQ pins and second DQ pins) for receiving operation codes. This segmentation allows different memory devices or different function groups to be configured simultaneously through different pins, thereby reducing the total configuration time while supporting multiple functions.
Solution Approach 2:
The patent enables preliminary configuration of mode registers by allowing operation codes to be transmitted and stored before actual data operations begin. The mode registers are set in advance through dedicated data input/output pins, preparing the memory devices for high-speed operations without delaying the main data processing workflow.
2Quantity of substance
If multiple memory devices are used, then memory capacity and performance are improved, but total time to set mode registers increases
Solution Approach 1:
The patent assigns different data input/output pins to different memory devices or device groups, enabling parallel configuration. For example, first DQ pins can configure first memory devices while second DQ pins simultaneously configure second memory devices, thus scaling memory capacity without linearly increasing configuration time.
Solution Approach 2:
The patent combines multiple configuration operations into a single unified process by using a shared command structure (mode register update command) that can trigger simultaneous configuration across multiple devices through different data pins, reducing overhead and coordinating multi-device setup efficiently.
3Loss of time
If separate data input/output pins are used for receiving operation codes, then configuration time is reduced, but device complexity increases
Solution Approach 1:
The patent makes existing data input/output pins multi-functional by enabling them to receive both operation codes for mode register configuration and actual data for memory operations. The same physical pins serve dual purposes: configuration mode (receiving operation codes) and data mode (receiving/writing data), thereby reducing the need for additional dedicated configuration pins.
Solution Approach 2:
The patent inverts the traditional approach by using data pins (typically used for data transfer) to carry operation codes for configuration. Instead of having separate dedicated configuration pins, the system repurposes the high-speed data pins to perform both configuration and data operations, leveraging the existing data path infrastructure.
Data Source
AI summary
A memory device including: a memory cell array; a first data input/output pin through which a first signal is input or output, wherein the first signal includes first bits to be written in the memory cell array or output from the memory cell array; a second data input/output pin through which a second signal is input or output, wherein the second signal includes second bits to be written in the memory cell array or output from the memory cell array; a first receiver configured to receive first operation codes for the first signal through the first data input/output pin; a second receiver configured to receive second operation codes for the second signal through the second data input/output pin; a first mode register configured to store the first operation codes; and a second mode register configured to store the second operation codes.