Back-Gate NOSRAM Read Cell for Stable Bit Line Sensing
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Solution Overview
Problem
The reliability of data reading in NOSRAM devices using OS transistors is compromised due to variations in bit line potential, leading to potential malfunctions and reduced memory density, while high power consumption is a concern.
Innovation Solution
A semiconductor device with a memory cell structure comprising a first and second transistor, where the gate electrode of the first transistor is connected to a write word line, and the back gate electrode of the second transistor is connected to a control signal line, allowing for controlled threshold voltage adjustment through specific signal levels during data reading and writing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a two-transistor memory cell structure is used, then the number of elements per memory cell is reduced, but data reliability is compromised due to bit line potential variations
Solution Approach 1:
The patent applies parameter changes by introducing a back gate electrode to the second transistor, enabling dynamic control of the threshold voltage. This allows the transistor's electrical characteristics to be adjusted in response to bit line potential variations, thereby maintaining reliable data reading operations while using a compact two-transistor memory cell structure.
Solution Approach 2:
The patent implements dynamics by making the threshold voltage of the second transistor可调 (adjustable) through the back gate electrode connected to a control signal line. This dynamic adjustment capability allows the memory cell to adapt its operating parameters based on real-time conditions, ensuring reliable data reading despite potential bit line variations.
2Device complexity
If conventional reading control is used, then device complexity is reduced, but power consumption increases due to uncontrolled current flow
Solution Approach 1:
The patent uses parameter changes by controlling the threshold voltage of the second transistor through the back gate electrode. By adjusting this parameter based on selection signals, the device enables precise control of current flow during reading operations, reducing unnecessary power consumption while maintaining manageable device complexity.
3Ease of operation
If threshold voltage is not controlled, then ease of operation is improved, but memory density decreases due to larger cell size requirements
Solution Approach 1:
The patent applies parameter changes through the back gate electrode mechanism, which dynamically adjusts the threshold voltage of the second transistor. This enables reliable operation with compact cell dimensions, thereby increasing memory density while maintaining ease of operation through automated control signals.
Data Source
AI summary
A semiconductor device that is highly integrated and reliable is provided. A back gate electrode of a second transistor is electrically connected to a control signal line supplying a control signal controlling the threshold voltage of the second transistor. One of a source and a drain of the second transistor is electrically connected to a read word line supplying a read word signal. The other of the source and the drain of the second transistor is electrically connected to a read bit line reading a potential corresponding to data. In a memory cell selected in a data reading period, a low level is supplied as the read word signal and a high level is supplied as the control signal. In the memory cell not selected in the data reading period, a high level is supplied as the read word signal and a low level is supplied as the control signal.