SOT-MRAM Write Current Pulse Trailing Edge Control
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Solution Overview
Problem
SOT magneto resistive memory devices with perpendicular magnetic anisotropy suffer from high write error rates due to the 'switch back' effect, which is sensitive to manufacturing and operational variations, as well as external magnetic fields, making precise control of the write current pulse duration challenging, especially at high current densities.
Innovation Solution
The solution involves configuring the write current pulse with a longer trailing edge, where the current remains greater than 30% of the maximum value 1 ns after the trailing edge starting time, and optionally greater than 60% or 80%, to reduce the switch back effect and enhance write error rate performance across a wider range of current pulse maximum values.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a conventional current pulse with short trailing edge is used, then the write operation is fast, but the write error rate is high due to switch back effect
Solution Approach 1:
The patent applies periodic action by using a current pulse with a specific temporal structure - a rising edge followed by a controlled trailing edge that maintains current above 30% of maximum for at least 1 ns. This periodic temporal pattern prevents the switch back effect while enabling reliable state writing in SOT-MRAM cells.
Solution Approach 2:
The patent changes the temporal parameters of the write current pulse, specifically controlling the trailing edge duration and magnitude. By maintaining the current above 30% of its maximum value for at least 1 ns after the trailing edge starts, the patent optimizes the pulse shape to prevent magnetization switching errors without requiring excessively long pulse durations.
2Reliability
If the current pulse maximum value is increased to overcome switch back effect, then the write reliability improves, but the sensitivity to manufacturing and operational variations increases
Solution Approach 1:
The patent changes multiple parameters of the write current pulse simultaneously - not just the maximum value but also the trailing edge duration and the time profile. By controlling the trailing edge to maintain current above 30% of maximum for at least 1 ns, the patent creates a more robust write operation that is less sensitive to variations in cell characteristics, manufacturing tolerances, and operational conditions.
Solution Approach 2:
The patent applies preliminary action by carefully shaping the current pulse before the actual magnetization switching occurs. The controlled trailing edge serves as a preparatory phase that ensures the magnetization transition is completed reliably before the current drops, preventing switch back effects and reducing sensitivity to subsequent variations.
3Reliability
If the trailing edge of the current pulse is extended to reduce switch back effect, then the write error rate decreases, but the write operation duration increases
Solution Approach 1:
The patent optimizes the temporal parameters of the current pulse by extending the trailing edge duration to at least 1 ns while maintaining the current above 30% of maximum. This specific parameter configuration achieves reliable writing without excessive time penalty, balancing write reliability with operational speed in SOT-MRAM devices.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces the write error rate and makes the memory device more robust to manufacturing and operational variations, while also minimizing sensitivity to external magnetic fields, allowing for reliable state storage across a broader range of current pulse values.
Implementation Method 1
The current flowing in the SOT current layer generates spin-orbit torques that aim at changing the magnetization orientation of the free layer 2b
Implementation Method 2
The resistance value between the reference layer 2c and the free layer 2b is dependent on the state of the free layer magnetization orientation. When the free layer 2b and the reference layer 2c have parallel magnetizations, the magnetic tunnel junction presents a relatively lower electric resistance, whereas in the antiparallel magnetizations the magnetic tunnel junction presents a relatively higher electric resistance
Data Source
Figure 1a~2a
Figure 2b~4
Figure 5a~5d
AI summary
The invention concerns a current signal for writing a state in at least one SOT memory cell of a magnetic memory device. The current signal comprises a rising edge to elevate the current to a first maximum value and a trailing edge to reduce, from a trailing edge starting time, the current from the maximum value. According to the invention the current, 1 ns after the trailing edge starting time, is greater than 30% of the first maximum value. The invention also related .to a magnetic memory device and to a method for writing a first state in at least one SOT memory cell of a magnetic memory device.