Stacked SRAM Cells With Complementary Layered Transistor Layout
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Solution Overview
Problem
Conventional semiconductor designs face challenges in achieving desired levels of miniaturization due to non-optimized arrangements of NFETs and PFETs in static RAM cell structures, which hinder spatial efficiency.
Innovation Solution
A stacked cell structure with complementary adjacent cells, where each cell spans multiple layers, with varying numbers of NFETs and PFETs on each layer, allowing for optimized spatial arrangements and miniaturization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional SRAM cell structures with four NFETs and two PFETs are used, then the cell can maintain proper functionality, but the spatial arrangement is not optimized leading to larger area occupation
Solution Approach 1:
The patent transitions from a planar two-dimensional layout to a three-dimensional stacked configuration where transistors are arranged across multiple layers vertically. The first cell has NFETs on a first layer and PFETs on a second layer, while the second cell has PFETs on the first layer and NFETs on the second layer, effectively utilizing the vertical dimension to reduce footprint area.
Solution Approach 2:
The patent employs asymmetric complementary arrangement where adjacent cells have inverted transistor distributions across layers. The first cell contains more NFETs on the first layer while the second cell contains more PFETs on the first layer, creating an asymmetric pattern that optimizes spatial utilization and reduces overall cell area compared to symmetric conventional designs.
2Productivity
If the number of NFETs and PFETs is varied between adjacent cells, then spatial optimization is achieved, but the cell structure becomes more complex
Solution Approach 1:
The patent divides the transistor distribution into segmented layers, with each layer containing a specific subset of transistors. The first layer contains NFETs for the first cell and PFETs for the second cell, while the second layer contains PFETs for the first cell and NFETs for the second cell, creating a segmented vertical architecture that improves spatial efficiency.
Solution Approach 2:
The patent merges the first and second cells into a shared vertical structure spanning two layers, where both cells utilize the same physical space but with complementary transistor assignments. This merging approach allows efficient packing of multiple functional cells within a reduced area while maintaining distinct operational characteristics through the complementary transistor distribution.
Data Source
AI summary
A field effect transistor (FET) cell structure of an integrated circuit (IC) is provided. The FET cell structure includes first and second adjacent cells. Each of the first and second adjacent cells spans a first layer and a second layer. The second layer is vertically stacked on the first layer. The first cell includes n-doped FETs (NFETs) on one of the first and second layers and p-doped FETs (PFETs) on another of the first and second layers. The second cell includes at least one of a number of NFETs on the one of the first and second layers differing from a number of the NFETs in the first cell and a number of PFETs on the another of the first and second layers differing from a number of the PFETs in the first cell.