Common Protocol Interface for Chiplet Data Communication
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Solution Overview
Problem
Current technologies lack a common interface for efficient data communication between chiplets on an interposer, leading to system performance degradation and limited scalability, especially in integrating chiplets from different vendors into a single high-performance system.
Innovation Solution
A common protocol interface (CPI) circuitry is developed to enable efficient data communication between chiplets on an interposer, providing low latency, high bandwidth, and scalable bandwidth, along with a low power physical layer, allowing chiplets to function as a single high-performance system with minimal performance degradation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If existing interface standards are used for data communication between chiplets on an interposer, then communication functionality is provided, but system performance degrades and scalability is limited
Solution Approach 1:
The patent segments the communication interface into standardized functional blocks (physical layer, link layer, transaction layer) that can be independently designed and optimized. This segmentation allows each layer to be tailored for high-performance chiplet communication while maintaining overall system reliability through modular architecture.
Solution Approach 2:
The CPI interface is designed as a universal standard that can accommodate multiple chiplet types and vendors through a common protocol framework. This multi-functionality enables different chiplet configurations (sensors, compute elements, memory) to interoperate seamlessly, improving productivity without compromising reliability.
2Adaptability or versatility
If chiplets from different vendors are integrated into a single system, then system functionality and scalability are improved, but interface compatibility and performance consistency become problematic
Solution Approach 1:
The CPI interface defines a universal protocol that works across chiplets from different vendors. The standardized physical layer, link layer, and transaction layer ensure that any compliant chiplet can communicate reliably, achieving both adaptability and performance consistency.
Solution Approach 2:
The interface allows parameter configuration (bandwidth, latency, power mode) to be adjusted based on specific chiplet requirements while maintaining protocol compatibility. This enables performance optimization for different vendor chiplets without sacrificing reliability.
3Productivity
If high bandwidth communication is implemented between chiplets, then data transfer capability is improved, but power consumption increases
Solution Approach 1:
The CPI interface implements dynamic power management where bandwidth and power consumption are adjusted based on actual communication needs. The physical layer can transition between high-performance modes (when data transfer is required) and low-power modes (during idle periods), achieving both high bandwidth capability and energy efficiency.
Solution Approach 2:
The interface uses periodic training and negotiation sequences to establish communication parameters, followed by sustained high-bandwidth transfer only when needed. This periodic activation of high-performance modes reduces overall power consumption while maintaining the capability for high bandwidth when required.
4Loss of time
If low latency communication is achieved between chiplets, then system response time is improved, but complexity of the interface protocol increases
Solution Approach 1:
The protocol is segmented into three layers, each handling specific functions. The physical layer manages signal timing for low latency, the link layer handles flow control, and the transaction layer manages data exchange. This segmentation reduces overall complexity by distributing functionality across layers while achieving low latency through optimized physical layer design.
Data Source
AI summary
A representative system, apparatus, method and protocol are disclosed for data communication between chiplets or SOCs on a common interposer. A representative system comprises: an interposer; a first integrated circuit arranged on the interposer, the first integrated circuit comprising a first common protocol interface circuit; a communication link coupled to the first common protocol interface circuit; and a second integrated circuit arranged on the interposer, the second integrated circuit comprising a second common protocol interface circuit coupled to the communication link to form a serial protocol interface between the first common protocol interface circuit and the second common protocol interface circuit. Serial data and control packets and parallel data and control packets having specified, ordered fields are also disclosed.