SRAM Subarray Voltage Boost for Access Reliability
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Solution Overview
Problem
Existing SRAM arrays face challenges in maintaining access reliability due to variability in fabrication tolerances and operating conditions, leading to potential corruption of memory states during read and write operations, especially at lower supply voltages, and existing voltage assist mechanisms are power-intensive and inefficient.
Innovation Solution
The method involves selectively applying a voltage boost to a first negative supply voltage of a subarray within an SRAM array, dynamically adjusting it to be lower than a second negative supply voltage, using capacitive pump circuitry distributed within the row decoder circuitry, thereby eliminating the need for an auxiliary supply and reducing energy consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If voltage assist circuitry is applied to all storage cells in a memory array, then access reliability is improved, but the assist circuitry becomes relatively large and consumes significant power
Solution Approach 1:
The memory array is divided into multiple subarrays, and voltage assist is applied selectively to only those subarrays that require it based on access patterns and operational conditions. This segmentation allows the system to maintain reliability where needed while avoiding unnecessary power consumption in subarrays that do not require assist.
Solution Approach 2:
Different subarrays receive different voltage assist treatments based on their specific operational requirements. The system dynamically adjusts which subarrays receive voltage boost, creating local quality variations in assist application rather than uniform assistance across the entire array, thereby optimizing the balance between reliability and power consumption.
2Productivity
If voltage assist circuitry is applied to all storage cells, then the ability to read from and write to SRAM cells is improved, but the circuitry size increases significantly
Solution Approach 1:
The memory array is segmented into multiple subarrays with independent voltage assist control. By enabling assist only in specific subarrays that require enhanced read/write capability, the system achieves high productivity where needed while minimizing the overall circuitry area occupied by assist structures.
Solution Approach 2:
Instead of applying voltage assist universally to all subarrays, the system applies partial assistance only to the extent necessary for maintaining reliable operation. This partial action approach ensures adequate read/write ability is achieved while avoiding the excessive circuitry area that would result from comprehensive assist coverage.
3Reliability
If existing voltage assist mechanisms are used, then access reliability is improved, but power consumption increases significantly
Solution Approach 1:
The voltage assist is applied periodically and dynamically based on actual access requirements rather than continuously. The control logic monitors operational conditions and activates voltage boost only during periods when it is needed for maintaining reliability, thereby significantly reducing overall power consumption compared to continuous assist mechanisms.
Solution Approach 2:
The system incorporates intelligent control logic that automatically determines when and where voltage assist is needed based on monitored operational parameters. This self-service capability allows the system to optimize the balance between reliability and power consumption without external intervention, activating assist only when naturally required by operational conditions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances read and write operations by improving current conduction and reducing the risk of memory state corruption, while minimizing power consumption and size requirements by applying voltage boost only to specific subarrays as needed.
Implementation Method 1
using capacitive pump circuitry distributed within the row decoder circuitry
Data Source
AI summary
A method and a system are provided for performing memory access assist using voltage boost. A memory access request is received at a storage cell array that comprises two or more subarrays, each subarray including at least one row of storage cells. The voltage boost is applied, during the memory access, to a first negative supply voltage of a first storage cell subarray of the two or more storage cell subarrays. The first negative supply voltage of the first storage cell subarray is lower than a second negative supply voltage of a second storage cell subarray of the two or more storage cell subarrays.


