Clock Generation Circuit With Reset Feedback for Pulse-Width Control
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Solution Overview
Problem
Existing memory devices require a clock generation circuit that can generate an internal clock signal with a specified pulse width efficiently to synchronize operations with high-speed CPUs, minimizing delay time and enabling independent control of internal circuits.
Innovation Solution
A clock generation circuit comprising a latch circuit, NAND gate, generation circuit, and reset circuit that generates an internal clock signal with a specified pulse width by using an enable signal, inverse internal clock signal, and a reset signal to control the pulse width, reducing delay time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If a conventional clock generation circuit is used, then the circuit can generate internal clock signals, but the delay time to generate the signal with specified pulse width is excessive
Solution Approach 1:
The clock generation circuit is divided into multiple functional blocks: a latch circuit for signal conditioning, a NAND gate for pulse width determination, and a reset circuit for timing control. This segmentation allows each block to perform its function efficiently, reducing overall delay time compared to a conventional unified circuit design.
Solution Approach 2:
The latch circuit performs preliminary processing on the clock signal and enable signal before they reach the NAND gate. By pre-conditioning the signals (clamping voltage levels and preparing logic states), the latch circuit reduces the processing time required by subsequent stages, thereby reducing total delay time.
2Adaptability or versatility
If the pulse width of the internal clock signal is extended to accommodate circuit operations, then more circuits can be controlled, but the delay time increases
Solution Approach 1:
The reset circuit uses the inverted internal clock signal as feedback to automatically terminate the pulse width. When the internal clock signal goes high, its inverted version triggers the reset circuit after a predetermined time, which then resets the generation circuit. This feedback mechanism precisely controls pulse width without requiring manual timing adjustments that would increase delay.
Solution Approach 2:
The circuit dynamically controls the pulse width parameter of the internal clock signal by using the reset signal to change the state of the generation circuit. The pulse width is determined by the predetermined time constant of the reset circuit rather than being fixed, allowing adaptation to different operational requirements while maintaining minimal delay.
Data Source
AI summary
A clock generation circuit generates an internal clock signal with a specified pulse width in response to a clock signal and an enable signal. The clock generation circuit includes a latch circuit receiving the clock signal, the enable signal, and an inverse internal clock signal and outputs a first signal, a NAND gate performing a NAND operation on the clock signal and the first signal to output a second signal, a generation circuit outputting the internal clock signal based on the second signal, and a reset circuit connected to the generation circuit and outputting a reset signal after a second time corresponding to the specified pulse width elapses from a point in time when the internal clock signal transitions to a high level. The inverse internal clock signal is generated by inverting and delaying the internal clock signal as much as a first time.