Multi-Capacitor Memory Bit-Cell Layout for Lower Leakage Sensing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Memory bit-cells with multiple capacitive devices face increased transistor size due to threshold voltage variation, leading to higher capacitive load on sense-lines or bit-lines, which reduces sensing noise margin and impairs data detection accuracy.
Innovation Solution
A multi-element gain bit-cell design incorporating a non-linear polar material, such as ferroelectric or paraelectric capacitors, with a shared gain transistor and individual access transistor, arranged in stacked or folded configurations, reduces leakage through the sense-line by controlling the first transistor, thereby increasing the sense margin.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple capacitive devices are used in a bit-cell, then storage capacity is improved, but transistor size increases leading to higher capacitive load on sense-lines
Solution Approach 1:
The patent divides the bit-cell into multiple independent capacitive devices (first capacitor and second capacitor), each capable of storing data independently. This segmentation allows the bit-cell to achieve higher storage capacity while managing transistor size through shared access mechanisms, resolving the contradiction between storage capacity and device complexity.
Solution Approach 2:
The patent merges the access control functions for multiple capacitive devices by implementing shared sense-lines and shared bit-lines. This combining approach reduces the overall transistor count and size required compared to having dedicated access transistors for each capacitor, thereby reducing capacitive load on sense-lines while maintaining multi-capacitor storage capacity.
2Reliability
If transistor size increases to accommodate multiple capacitive devices, then threshold voltage variation is reduced, but capacitive load on sense-lines increases reducing sensing noise margin
Solution Approach 1:
The patent implements partial action by having only one access transistor per capacitive device rather than full dedicated control for each capacitor. The shared sense-line and selective activation of capacitors means that not all capacitive devices are accessed simultaneously, effectively reducing the total capacitive load on sense-lines during any given operation while maintaining threshold voltage stability through proper transistor sizing for the active device.
3Quantity of substance
If multiple capacitive devices are used, then data storage density is improved, but leakage through sense-line increases
Solution Approach 1:
The patent implements periodic action through selective activation of capacitive devices using word-lines. Only the capacitor corresponding to the selected word-line is activated and accessed during any given operation cycle. This periodic, selective activation ensures that leakage current flows through only one capacitor at a time rather than through all capacitors simultaneously, reducing total leakage through sense-lines while maintaining high data storage density through the multi-capacitor architecture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design enhances sensing accuracy by reducing leakage and increasing the sense margin, improving data detection in memory bit-cells with multiple capacitive devices.
Implementation Method 1
non-linear polar material, such as ferroelectric or paraelectric capacitors
Implementation Method 2
non-linear polar material, such as ferroelectric or paraelectric capacitors
Implementation Method 3
multi-capacitor bit-cell with shared gain element
Data Source
AI summary
Described herein is a memory bit-cell that results in lower leakage and higher sensing margin. In at least one embodiment, a memory bit-cell comprises a plurality of capacitors, wherein an individual capacitor is coupled to a node and an individual plate-line. In at least one embodiment, memory bit-cell comprises a first transistor coupled to the node. In at least one embodiment, memory bit-cell comprises a second transistor coupled in series with the first transistor, wherein the second transistor is coupled to a bit-line, wherein the first transistor or the second transistor is controllable by a word-line, and wherein the word-line is parallel to the individual plate-line.