Cross-Point Memory Voltage Generation Circuit
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Solution Overview
Problem
Conventional voltage systems and power source devices are not suitable for low current consumption and high-speed stable operation in nonvolatile memory devices due to their inability to achieve high-speed rising of output voltage during start-up.
Innovation Solution
A cross-point variable resistance nonvolatile memory device incorporating a cross-point memory cell array with variable resistance elements and current steering elements, along with a column decoder, pre-charge circuit, low decoder driver, feedback controlled bit line voltage clamp circuit, and sense amplifier circuit, which enables high-speed reading by setting optimal voltages and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a conventional voltage system with differential amplifier and bias circuit is used, then the read operation voltage can be compensated for threshold voltage changes, but the system cannot achieve high-speed rising of output voltage during start-up and consumes more power
Solution Approach 1:
The patent extracts and removes the differential amplifier and bias circuit from the conventional voltage system, replacing them with a simplified voltage generation circuit that directly generates the read operation voltage without complex feedback mechanisms, thereby achieving fast voltage rising and low power consumption
Solution Approach 2:
The voltage generation circuit is designed to automatically generate the appropriate read voltage based on the selected memory cell characteristics without requiring external bias circuits or differential amplification, making the system self-sufficient and efficient
2Reliability
If a conventional voltage system with differential amplifier is used, then voltage compensation can be achieved, but the system complexity increases and high-speed operation is not possible
Solution Approach 1:
The patent removes the differential amplifier and bias circuit components, simplifying the circuit architecture while maintaining voltage stability through a more direct voltage generation approach that eliminates complex feedback loops
Solution Approach 2:
The voltage generation is segmented into discrete, controllable stages through the use of switching elements and resistance elements, allowing precise voltage control without requiring complex integrated circuits
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables high-speed and stable operation with reduced power consumption by quickly setting the best voltage linked to the current steering element characteristics, allowing frequent start-stop operations without sacrificing stability and reducing voltage shifts during read operations.
Implementation Method 1
A variable resistance element is an element that has a property that a resistance value changes (reversibly changes between a high resistance state and a low resistance state) according to an electrical signal
Implementation Method 2
a current steering element that is connected in series with the variable resistance element and has nonlinear current-voltage characteristics
Implementation Method 3
a feedback controlled bit line voltage clamp circuit which sets the selected bit line to a second voltage and maintains the second voltage in the second pre-charge period and the sense period
Implementation Method 4
a sense amplifier circuit which determines in the sense period, according to an amount of current flowing through the selected memory cell, whether the variable resistance element in the selected memory cell is in the low resistance state or the high resistance state
Data Source
AI summary
A cross-point variable resistance nonvolatile memory device comprises: a memory cell array; a column decoder and pre-charge circuit which pre-charges a selected word line to a first voltage in a period P1 among the period P1, a period P2, and a period S that are included in this order in a read operation of a memory cell; a low decoder driver which pre-charges a selected word line to the first voltage in the periods P1 and P2 and sets the selected word line to a third voltage different from the first voltage in the period S; a feedback controlled bit line voltage clamp circuit which sets the selected bit line to a second voltage in the periods P2 and S; and a sense amplifier which determines the resistance state in a memory cell at a cross-point of the selected word line and the selected bit line in the period S.