Capacitor-Free Memory Cell Stack for Stable Low-Power DRAM
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Solution Overview
Problem
Existing semiconductor devices with memory functions face challenges in memory performance, cell stability, reliability, and power efficiency due to the design and placement of memory cells, particularly in dynamic random access memory (DRAM) devices.
Innovation Solution
The semiconductor device replaces capacitors in memory cells with transistors and employs a stacked structure of multiple transistors, utilizing oxide semiconductors like In—Sn—Ga—Zn—O for improved performance, and includes a specific gate and interconnect structure to enhance data storage and retrieval operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If capacitors are used to store data in memory cells, then data storage function is achieved, but device complexity and area occupation increase
Solution Approach 1:
The patent extracts and removes the capacitor component from the memory cell structure. Instead of using a separate capacitor for data storage, the invention utilizes the gate structure of transistors themselves to store data, thereby eliminating the need for dedicated capacitor components and simplifying the overall memory cell architecture.
Solution Approach 2:
The transistor gate structures serve multiple functions: they act as both the control element for transistor operation and the data storage element. The gates can store data through their electrical state while simultaneously controlling current flow, combining storage and control functions in a single component rather than requiring separate capacitor and transistor elements.
2Productivity
If traditional DRAM cell design is used, then manufacturing process is established, but memory performance and power efficiency are limited
Solution Approach 1:
The patent changes the fundamental parameters of the memory cell by transitioning from capacitor-based storage to transistor gate-based storage. This parameter change enables new operational modes where data is stored in the electrical state of transistor gates rather than charge accumulation in capacitors, leading to improved performance metrics and reduced power consumption through different refresh and access mechanisms.
3Quantity of substance
If multiple transistors are stacked in memory cells, then integration density increases, but manufacturing precision requirements increase
Solution Approach 1:
The patent merges multiple transistor structures into a stacked configuration where transistors are vertically integrated rather than planarly arranged. By combining the storage and control functions within this stacked transistor architecture, the design achieves higher integration density while the unified structure reduces the number of separate interconnect layers needed compared to traditional lateral arrangements.
Data Source
AI summary
A semiconductor device including one or more memory cells and a method for operating the same are disclosed. Each of the memory cells includes a first transistor configured to write data, a second transistor configured to store the data, and a third transistor configured to refresh the data. The memory cell includes a first transistor including a first gate connected to a write word line and one terminal connected to a storage node, a second transistor including a second gate connected to the storage node and one terminal connected to a read word line and a third transistor including a third gate connected to the read word line and one terminal connected to a read bit line.