FinFET Gate Oxide and Junction Layout for HCI and GIDL Reliability
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Solution Overview
Problem
FINFET elements operating under high voltage conditions face reliability issues due to Hot Carrier Injection (HCI) and Gate Induced Drain Leakage (GIDL) characteristics.
Innovation Solution
The semiconductor device incorporates FINFET elements with source and drain regions having different structures, reducing the electric field around overlapping regions by varying their dimensions, doping concentrations, and gate dielectric layer thickness based on voltage requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate dielectric layer thickness is increased to reduce GIDL, then the device reliability improves, but the device complexity increases due to different thickness requirements for different elements
Solution Approach 1:
The patent applies local quality by differentiating the gate dielectric layer thickness across different semiconductor elements. Specifically, the first semiconductor element has a gate dielectric layer with a first thickness, while the second semiconductor element has a gate dielectric layer with a second thickness that is greater than the first thickness. This localized variation optimizes each element's performance for its specific function, reducing GIDL in high-voltage elements while maintaining HCI performance in low-voltage elements.
Solution Approach 2:
The patent segments the gate dielectric layer into multiple regions with different thicknesses corresponding to different semiconductor elements. The gate dielectric layer is divided such that portions over different element regions have distinct thickness characteristics, allowing independent optimization of each segment's electrical properties without affecting other segments.
2Reliability
If the source and drain regions have different structures to reduce electric field, then HCI characteristics improve, but the manufacturing precision requirements increase
Solution Approach 1:
The patent implements asymmetry by creating non-uniform source and drain region structures. The source region and drain region are configured with different dimensions, doping concentrations, or geometrical shapes, breaking the symmetry to reduce peak electric field intensity. This asymmetric design mitigates HCI effects by distributing the electric field more evenly across the channel region.
3Reliability
If the gate dielectric layer thickness is varied to improve GIDL, then the device reliability improves, but the energy consumption increases due to higher voltage requirements
Solution Approach 1:
The patent applies local quality by varying the gate dielectric layer thickness specifically in regions where GIDL is problematic, rather than uniformly increasing thickness across all elements. This localized thickening reduces GIDL only where needed, minimizing the impact on overall device energy consumption while still improving reliability in critical areas.
Data Source
AI summary
A semiconductor device includes: a memory cell array region including memory cells connected to respective word lines and bit lines; and a peripheral circuit region including a first semiconductor element and a second semiconductor element. Each of the first and second semiconductor elements includes: a fin structure extending in a first direction on a substrate; a gate structure extending on the fin structure in a second direction, perpendicular to the first direction, and including a gate dielectric layer and a gate metal layer; and a source region and a drain region in the substrate at opposing ends of the fin structure. A thickness of the gate dielectric layer in the first semiconductor element is greater than a thickness of the gate dielectric layer in the second semiconductor element, and the source and drain regions in the first semiconductor element are doped with first conductivity type impurities and have different structures.