Multi-Port Memory Cell With Expandable Write Ports
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Solution Overview
Problem
Conventional semiconductor memory devices face challenges in consistently writing data at low voltages due to local mismatch variations in transistors, leading to issues like reduced drive current and increased power consumption, especially in multi-port SRAM memory cells, which require larger transistors to meet write margin and stability requirements.
Innovation Solution
The implementation of multi-port memory cells with an expandable port configuration, utilizing a pair of cross-coupled inverters and multiple write ports, each equipped with a drive control circuit that includes a write assist transistor and a drive transistor of opposite conductivity types, allowing for increased write ports without enlarging pass gate or pull-up transistor sizes, thus maintaining performance and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the number of write ports in a memory cell is increased to improve data access flexibility, then adaptability is improved, but device complexity increases due to larger transistor sizes required to maintain write margin and stability
Solution Approach 1:
The memory cell is segmented into multiple independent write ports (first write port, second write port, etc.), each with its own drive control circuit. This segmentation allows each port to be controlled independently while sharing common memory cell resources, enabling increased adaptability without proportional increases in overall device complexity
Solution Approach 2:
The drive control circuit is designed with multi-functionality to handle multiple write ports. The same drive control circuit structure can control different write ports by selectively enabling appropriate transistors, reducing the need for separate control circuits for each port and thereby limiting the increase in device complexity
2Reliability
If transistor sizes are increased to maintain write margin and stability in multi-port SRAM cells, then reliability is improved, but manufacturing precision becomes more difficult due to tighter process control requirements
Solution Approach 1:
The invention changes the operational parameters of the memory cell by introducing controlled voltage levels (first voltage, second voltage, third voltage) to different nodes during write operations. By dynamically adjusting voltage parameters rather than relying solely on fixed transistor sizes, the design achieves improved write margin and stability while avoiding the manufacturing precision challenges associated with larger transistors
3Reliability
If larger transistors are used in multi-port SRAM cells to meet write requirements, then power consumption increases, but write capability is maintained
Solution Approach 1:
The drive control circuit employs periodic action by selectively enabling write operations through controlled voltage transitions. The circuit applies voltages to bitlines and wordlines only when write operations are needed, rather than maintaining continuous high current flow. This periodic activation maintains write capability while significantly reducing overall power consumption compared to continuously active larger transistors
Data Source
AI summary
A memory device includes a memory array comprising a plurality of memory cells. At least one of the memory cells comprises a pair of cross-coupled inverters, and a plurality of ports, including at least one write port. A given write port comprises at least one drive control circuit having an output coupled to respective gate terminals of both a write assist transistor and a drive transistor, with the write assist transistor being arranged in series with one of a pull-up and a pull-down path of a corresponding one of the inverters, and the drive transistor being configured to hold one of the internal nodes at a designated logic level in conjunction with a write operation. First and second drive control circuits of this type may generate complementary control signals for application to respective pairs of write assist and drive transistors associated with respective ones of the inverters.