Memory Signal Boosting Circuit for Long Metal Line RC Delay
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Solution Overview
Problem
The time required for discharge and pre-charge of long metal lines in memory devices is limited by parasitic wire resistance and capacitance (RC), affecting memory performance.
Innovation Solution
A signal boosting circuit is introduced at a middle portion of the long metal line to sense rise/fall transitions and enable stronger Pull Up (PU) and Pull Down (PD) circuits, controlled by a control signal to speed up transitions and reduce RC impact.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a long metal line (GRBL) is used to transmit binary signals in a single ended manner, then the memory device can maintain simple circuit structure, but the parasitic wire resistance and capacitance increase causing slower discharge and pre-charge times
Solution Approach 1:
The patent divides the long metal line into multiple segments by introducing a signal boosting circuit at an intermediate point. This segmentation allows the long wire to be treated as shorter effective segments, reducing the impact of parasitic RC effects on signal transition times while maintaining the overall single-ended architecture.
Solution Approach 2:
The signal boosting circuit acts as an intermediary element inserted into the long metal line. This intermediary actively senses voltage transitions and provides boosted drive strength to overcome the cumulative parasitic effects of the long wire, enabling faster signal propagation without changing the fundamental single-ended topology.
2Adaptability or versatility
If the metal line length is increased to connect more memory cells, then more memory cells can be accessed, but the parasitic wire RC increases limiting memory performance
Solution Approach 1:
By segmenting the long metal line with a signal boosting circuit, the patent enables the system to support longer wire lengths (connecting more memory cells) without proportionally degrading performance. The boosting circuit effectively resets the RC time constant accumulation at the intermediate point.
Solution Approach 2:
The signal boosting circuit dynamically changes the effective drive strength parameter along the metal line. By providing additional current drive at the intermediate point, it compensates for the increased parasitic RC effects that would otherwise limit performance in longer wire configurations.
3Speed
If stronger Pull Up and Pull Down circuits are used to speed up transitions, then the discharge and pre-charge time decreases, but the circuit complexity and power consumption increase
Solution Approach 1:
Instead of strengthening all pull-up and pull-down circuits throughout the entire memory array, the patent applies enhanced drive strength locally only at the intermediate signal boosting circuit position. This localized approach provides the necessary speed improvement while minimizing the addition of circuit complexity compared to a system-wide strengthening approach.
Data Source
AI summary
A memory device and its operation reduce the impact of a parasitic wire Resistance and Capacitance (RC) in the memory device. At least one of a rise transition and a fall transition of a signal transmitted by a long metal line is sensed by a sense circuit of a signal boosting circuit. At least one of a Pull Up (PU) circuit and a Pull Down (PD) circuit of the signal boosting circuit is enabled to speed-up one or both of the rise transition and the fall transition of the signal transmitted by the long metal line. The duration of an operation of one of the PU circuit and the PD circuit may be controlled using a control signal.