Semiconductor Memory Row Hammer Refresh Stabilization
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Solution Overview
Problem
As the number of memory cells in semiconductor memory apparatuses increases, the interval between word lines decreases, leading to a coupling phenomenon that destabilizes adjacent word lines during repeated write and read operations, resulting in data loss due to improper refresh operations.
Innovation Solution
A semiconductor memory apparatus and system that includes an address generation circuit to detect row hammering and generate a refresh target address for adjacent word lines, and an operation determination circuit to ensure the correct generation of this address through arithmetic operations and comparison, thereby stabilizing the refresh operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of memory cells is increased to improve storage capacity, then the interval between word lines decreases causing coupling phenomenon, but this leads to instability in adjacent word lines and data loss
Solution Approach 1:
The patent performs a refresh operation on the adjacent word line before the coupling phenomenon can cause data loss. The row hammer detection circuit detects when a word line is repeatedly accessed, and the refresh control circuit proactively refreshes the adjacent word line to prevent instability before it occurs.
Solution Approach 2:
The patent implements a feedback mechanism where the row hammer detection circuit monitors access patterns to word lines and provides feedback to the refresh control circuit. When repeated access is detected, the system automatically triggers a refresh operation on the adjacent word line to maintain stability.
2Reliability
If refresh operation is performed on adjacent word line to prevent data loss, then data safety is improved, but complexity of operation determination increases
Solution Approach 1:
The patent makes the memory system self-diagnostic and self-correcting. The row hammer detection circuit automatically detects access patterns and triggers appropriate refresh operations without external intervention. The operation determination circuit automatically determines whether a refresh operation is needed based on detected patterns.
Solution Approach 2:
The patent introduces intermediary circuits (row hammer detection circuit and operation determination circuit) that mediate between the memory access operations and the refresh control. These intermediary circuits analyze access patterns and provide control signals to the refresh control circuit, simplifying the overall control logic.
Data Source
AI summary
A semiconductor memory apparatus includes an address generation circuit and an operation determination circuit. The address generation circuit generates a refresh target address that corresponds to a word line, among a plurality of word lines, the word line being adjacent to another word line in which row hammering has occurred. The operation determination circuit configured to generate an address matching information by comparing a row hammering address with the refresh target address.