Flip-Flop Soft Error Correction via Clock Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Semiconductor integrated circuits, particularly flip flop circuits, face challenges with soft errors caused by radioactive rays, which are not adequately addressed by existing technologies, requiring effective error correction or detection mechanisms with minimal overhead.
Innovation Solution
A data storage circuit configuration that includes a clock control circuit, master and slave latch circuits, and an output data generation circuit, which shifts to a clock stop state to hold data and correct or detect errors using majority decision and error detection signals, allowing for efficient error handling with minimal overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an error correcting function is added to flip flop circuits, then soft errors can be corrected with small overhead, but device complexity increases
Solution Approach 1:
The circuit is divided into multiple latch circuits (first latch circuit and second latch circuit) that operate in parallel. Each latch circuit processes data independently through separate clock cycles, allowing error correction to be performed on segmented portions of data rather than requiring complex global error correction mechanisms.
Solution Approach 2:
The error correction function utilizes periodic clock signals (first clock signal and second clock signal) to alternately operate the first and second latch circuits. This periodic operation allows the same hardware structure to perform both normal data storage and error correction functions at different time periods, reducing overall device complexity.
2Reliability
If an error detecting function is added to flip flop circuits, then soft errors can be detected with small overhead, but device complexity increases
Solution Approach 1:
The second latch circuit serves multiple functions: it acts as a normal data storage element during regular operation and simultaneously functions as an error detection mechanism during correction cycles. The same circuit structure performs both data holding and error detection without requiring separate dedicated error detection hardware.
Solution Approach 2:
The latch circuits perform error detection and correction using their own internal structures and clocking mechanisms without requiring external error detection circuits. The circuit uses its redundant storage capability to automatically detect and correct errors through the periodic operation of the first and second latch circuits.
3Reliability
If multiple latch circuits are used for error correction, then error correction capability improves, but device complexity increases
Solution Approach 1:
The first and second latch circuits operate periodically with alternating clock signals, allowing the same physical hardware to serve different purposes at different times. This temporal multiplexing reduces the need for additional dedicated error correction circuits.
Solution Approach 2:
During error correction operation, the circuit temporarily discards normal data flow through the second latch circuit and recovers the original data from the first latch circuit after correction. This allows the use of existing latch circuit structures for error correction without permanently increasing the number of required storage elements.
Data Source
AI summary
Disclosed is a data storage circuit that stores target input data inputted to a data input terminal and outputs the stored data as target output data through a data output terminal. The data storage circuit includes a clock control circuit that outputs a master clock signal and a slave clock signal based on a reference clock signal, a master latch circuit that takes the target input data based on the master clock signal, holds the taken data, and outputs the taken data as master output data, a slave latch circuit that takes the master output data based on the slave clock signal, holds the taken data, and outputs the taken data as slave output data, and an output data generation circuit that generates the target output data.