3D Memory Gate Line Layout to Prevent Bridge Pattern Collapse

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Solution Overview

Problem

Existing semiconductor devices face challenges in maintaining reliability and preventing structural defects, such as pattern collapse, as the degree of integration increases with 3-dimensionally arranged memory cells.

Innovation Solution

The semiconductor device incorporates a structure with overlapping gate lines, dummy channel structures, and local word line cuts to define bridge connection portions, including normal and offset dummy channel structures, which enhance structural integrity and reduce the risk of pattern collapse during fabrication.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If the degree of integration increases with 3-dimensionally arranged memory cells, then data storage capacity increases, but structural defects such as pattern collapse occur

Engineering Contradiction:
Improvedata storage capacityVSAvoidstructural integrity
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The gate line is segmented into multiple portions (first gate line portion, second gate line portion, third gate line portion) separated by cut structures. This segmentation reduces the continuous length of gate lines, preventing pattern collapse while maintaining electrical connectivity through vertical connections to channel structures.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent transitions from planar gate line connections to three-dimensional connections by extending gate line portions vertically to contact channel structures at different levels. This dimensional change allows gate lines to be electrically connected without requiring long horizontal bridges, thereby preventing pattern collapse.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If gate lines are extended to connect main gate portions, then electrical connectivity is achieved, but pattern collapse risk increases

Engineering Contradiction:
Improveelectrical connectivityVSAvoidpattern stability
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The gate line is divided into discrete segments (first, second, and third gate line portions) that are electrically connected through vertical pathways via channel structures, rather than forming a continuous horizontal bridge. This segmentation eliminates the pattern collapse risk associated with long continuous gate line bridges.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Channel structures serve as intermediary elements that provide electrical connection between separated gate line portions. Instead of directly connecting gate lines horizontally (which causes pattern collapse), the channel structures mediate the electrical connection through vertical pathways.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If continuous gate lines are used to connect main gate portions, then electrical connection is maintained, but structural defects increase

Engineering Contradiction:
Improveelectrical connectionVSAvoidstructural complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The gate line architecture is segmented into multiple portions with cut structures, creating a modular design that reduces structural complexity. Each segment can be independently formed and controlled, simplifying the manufacturing process compared to forming long continuous gate lines with precise bridge connections.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent resolves structural complexity by moving electrical connections from the horizontal plane to the vertical dimension. Gate line portions connect to channel structures vertically, eliminating the need for complex horizontal bridge formations and reducing overall structural complexity.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS20260052689A1Semiconductor device and electronic system including the same
Publication Date: 2026.02.19 SAMSUNG ELECTRONICS CO LTD
  • US20260052689A1 patent drawing
  • US20260052689A1 patent drawing
  • US20260052689A1 patent drawing

AI summary

A semiconductor device includes gate lines each having a pair of main gate portions and a bridge connection portion, dummy channel structures passing through the gate lines in a vertical direction, and a local word line cut structure passing through respective local regions of the gate lines in the vertical direction and intermittently extending in a first direction to define the width of the bridge connection portion in the first direction, wherein the dummy channel structures include first normal dummy channel structures facing the local word line cut structure in a second direction and each having a center on an imaginary straight line extending in the first direction, and at least one offset dummy channel structure facing the bridge connection portion in the second direction and having a center at a position shifted from the imaginary straight line toward the bridge connection portion in the second direction.