Dual Redundant CAM Radiation Hardening via Parity Extraction
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Solution Overview
Problem
Content addressable memory (CAM) systems face issues with false match and false miss conditions due to errors in CAM cells, which existing error correction codes (ECCs) and triple mode redundancy (TMR) fail to effectively address, leading to increased power and area usage.
Innovation Solution
Implementing dual mode redundancy and a parity bit check to store CAM data in two redundant forms, where the parity bit is used to verify the correctness of the match, thereby minimizing or eliminating false matches and misses, and enhancing the memory's radiation hardness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If triple mode redundancy (TMR) is used to account for errors in CAM cells, then reliability is improved, but area and power usage increase significantly
Solution Approach 1:
The patent uses dual redundancy by storing the same CAM data in two separate CAM words (first CAM word and second CAM word) at different locations in the CAM array. This copying approach provides error mitigation similar to TMR but with reduced area overhead by using only two copies instead of three, and by sharing the RAM storage for the copied data.
Solution Approach 2:
The patent extracts the error detection function from the CAM match operation itself by introducing separate parity bits (first parity bit and second parity bit) that are stored independently in the RAM array. This separation allows parity checking to be performed independently from the match operation, enabling more efficient error detection without requiring the full TMR overhead in the CAM array.
2Reliability
If triple mode redundancy (TMR) is used to account for errors in CAM cells, then reliability is improved, but power consumption increases
Solution Approach 1:
The dual redundancy copying approach requires maintaining only two copies of CAM data instead of three, reducing the number of redundant storage locations and associated read/write operations. This directly reduces power consumption while maintaining error mitigation capability.
Solution Approach 2:
By extracting error detection to separate parity bits stored in RAM rather than embedding redundancy in the CAM structure, the patent reduces the power-intensive CAM operations. The parity check can be performed on already-retrieved data from RAM, avoiding additional high-power CAM access operations.
3Reliability
If error correction codes (ECCs) are used in CAM macros, then error correction capability is improved, but false match and false miss conditions increase
Solution Approach 1:
The patent introduces parity bits as intermediary error detection elements that operate independently from the CAM match operation. These parity bits serve as a mediator between the stored data and the match result, providing error detection without interfering with the fundamental CAM matching function. The match operation and parity check are separate stages, preventing false matches/misses from propagating.
Solution Approach 2:
The patent separates error detection (via parity bits) from the CAM match operation itself. This extraction ensures that the match operation remains precise and unaffected by error correction logic, while the parity check independently validates data integrity. This separation prevents the false match/miss conditions that occur when ECC logic is integrated into the CAM matching process.
Data Source
AI summary
A method for storing data includes determining, using a first match line, that a match word satisfies a first content addressable memory (CAM) word stored in a CAM array, wherein the CAM array is configured to store a second CAM word that matches the first CAM word. The method further includes determining that a first parity bit associated with the first CAM word matches a first parity of the first CAM word. The method further includes, in response to determining that the first parity bit associated with the first CAM word matches the first parity determining, using the first match line, a first random access memory (RAM) word stored in a RAM array and outputting the first RAM word.