Selective Row Refresh Circuit for Memory Data Integrity
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current memory systems face challenges in maintaining data integrity in rows physically adjacent to frequently accessed rows due to increased cell-to-cell leakage caused by coupling effects, which degrades data before normal refresh operations can occur.
Innovation Solution
The implementation of a refresh control circuit that selectively refreshes rows physically adjacent to a target row, using a multiplexer to provide either the target address, refresh address, or proximate address to the address bus, allowing for more frequent refreshes of adjacent rows during read, write, and refresh operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If normal refresh operations are performed on all rows at standard intervals, then overall memory refresh coverage is maintained, but rows physically adjacent to frequently accessed rows experience data degradation due to increased cell-to-cell leakage from coupling effects
Solution Approach 1:
The patent implements selective refresh operations that target only specific rows physically adjacent to frequently accessed rows, rather than uniformly refreshing all rows. This local quality approach applies different refresh frequencies to different memory rows based on their proximity to active rows, thereby improving data integrity in vulnerable adjacent rows without sacrificing overall refresh efficiency.
2Reliability
If refresh frequency is increased for all rows, then data integrity of adjacent rows is improved, but overall memory system performance and power consumption increase
Solution Approach 1:
The patent applies increased refresh frequency locally only to rows physically adjacent to frequently accessed rows, while maintaining standard refresh intervals for all other rows. This selective approach improves data integrity in vulnerable adjacent rows without causing system-wide performance degradation or excessive power consumption increases.
3Reliability
If selective refresh of adjacent rows is implemented, then data degradation in adjacent rows is reduced, but device complexity increases due to additional control circuitry
Solution Approach 1:
The patent segments the memory refresh control into distinct functional components: a frequency determination module that identifies frequently accessed rows, an address generation module that calculates addresses of physically adjacent rows, and a refresh control module that executes selective refresh operations. This segmentation manages device complexity by organizing the control logic into modular, manageable units.
Solution Approach 2:
The patent implements a feedback mechanism where the refresh control circuit monitors access patterns of memory rows and uses this information to dynamically adjust refresh operations for adjacent rows. The feedback loop continuously tracks which rows are frequently accessed and automatically triggers selective refresh operations on their adjacent rows, managing complexity through automated adaptive control.
Data Source
AI summary
Apparatuses and methods for selective row refreshes are disclosed herein. An example apparatus may include a refresh control circuit. The refresh control circuit may be configured to receive a target address associated with a target plurality of memory cells from an address bus. The refresh control circuit may further be configured to provide a proximate address to the address bus responsive, at least in part, to determining that a number of refresh operations have occurred. In some examples, a plurality of memory cells associated with the proximate address may be a plurality of memory cells adjacent the target plurality of memory cells.