Memory Output Pre-Driver Calibration for Stable Slew Rate
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in maintaining consistent slew rate due to process, voltage, and temperature variations, leading to issues with EMI measurements and data effective window attenuation, despite ZQ calibration efforts.
Innovation Solution
A memory device and method that adjusts driving strength of pre-drivers using a ZQ calibration signal to compensate for delay time variations, thereby controlling slew rate and reducing variations in output signal slew rate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ZQ calibration is used to reduce driving strength variation, then driving strength consistency is improved, but slew rate control circuit still generates additional current consumption and remains affected by PVT variations
Solution Approach 1:
The patent adjusts the driving strength of pre-drivers by changing the impedance parameter based on ZQ calibration signals. This allows the circuit to compensate for PVT variations and maintain consistent driving strength without requiring additional slew rate control circuits, thereby reducing current consumption while improving reliability
Solution Approach 2:
The patent extracts the slew rate control function from a separate control circuit and integrates it into the pre-driver stage through impedance adjustment. By taking out the dedicated control circuit, the patent eliminates the additional current consumption while maintaining the necessary slew rate control capability
2Power
If output stage circuit component size is determined at DC stage, then DC performance is optimized, but AC output slew rate becomes sensitive to PVT variations
Solution Approach 1:
The patent introduces dynamic adjustment capability to the pre-driver stage by using ZQ calibration signals to modify impedance based on operating conditions. This allows the circuit to adapt to PVT variations dynamically, maintaining stable slew rate performance across different voltage and temperature conditions while preserving DC optimization
Solution Approach 2:
The patent performs preliminary impedance adjustment in the pre-driver stage before the signal reaches the output stage. By pre-compensating for PVT variations through impedance modification, the circuit ensures stable slew rate performance without requiring changes to the output stage component sizes
Data Source
AI summary
A memory device and a method for controlling slew rate are disclosed. The memory device includes a memory array, a slew rate control circuit, and an output stage circuit. The memory array provides a data signal. The slew rate control circuit includes multiple pre-drivers. The slew rate control circuit receives a ZQ calibration signal and adjusts driving strength of each of the pre-drivers in the slew rate control circuit according to the ZQ calibration signal. The pre-drivers are configured to generate a driven enable signal according to the data signal. The output stage circuit generates a data voltage signal based on the driven enable signal and the data signal. The slew rate of the data voltage signal is adjusted based on the driving strength of the pre-drivers.