DRAM Row Hammer Polling and ALERT_n Mitigation
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Solution Overview
Problem
Existing methods for mitigating Row Hammer (RH) attacks in DRAM devices, such as error correction codes and increased refresh intervals, are inadequate and result in higher power consumption or performance degradation, while JEDEC standards like TTR and DDR5 are deficient for certain types of attacks.
Innovation Solution
Implementing two RH mitigation modes in DRAM: ALERT_n and polling, which include an active low signal for ALERT_n and a mode register bit for polling, allowing earlier detection and recovery, and supporting isochronous traffic bandwidth by limiting activations during recovery.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correction code (ECC) is used to mitigate RH attacks, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent segments the RH mitigation approach by introducing a dedicated RH detector component that operates independently from the main memory controller. This detector monitors row activation patterns and generates alerts specifically for RH attacks, separating the detection function from error correction functions while working together to improve reliability without proportionally increasing overall system complexity.
Solution Approach 2:
The patent introduces an intermediary RH detector that acts as a mediator between the memory controller and the RH attack threat. This detector intercepts and analyzes row activation patterns, generating alerts that trigger mitigation actions. This intermediary component simplifies the overall architecture by centralizing RH detection logic rather than distributing complexity across ECC and refresh mechanisms.
2Reliability
If memory refresh intervals are increased to mitigate RH attacks, then reliability is improved, but productivity decreases
Solution Approach 1:
The patent implements preliminary action by detecting RH attack patterns through continuous monitoring of row activation counts before actual bit flips occur. The RH detector identifies suspicious patterns and triggers alerts that enable proactive mitigation through targeted row refreshes, preventing attacks before they compromise data integrity while maintaining normal refresh intervals for optimal performance.
Solution Approach 2:
The patent applies dynamics by making the refresh strategy adaptive rather than static. The system dynamically adjusts refresh behavior based on real-time detection of RH attack patterns, performing targeted refreshes only when RH attacks are detected while maintaining standard refresh intervals during normal operation. This dynamic approach ensures reliability when needed while preserving productivity during normal memory operations.
3Reliability
If targeted row refresh (TTR) is implemented to mitigate RH attacks, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent implements self-service by enabling the RH detector to automatically monitor row activation patterns, identify RH attacks, and trigger targeted row refreshes without requiring complex external control logic. The detector autonomously manages the detection and mitigation process, reducing the need for additional hardware complexity while improving reliability through automated RH attack response.
4Reliability
If DDR5 RH mitigation measures are implemented, then reliability is improved, but they are deficient for some types of RH attacks
Solution Approach 1:
The patent applies parameter changes by making the RH detection and mitigation parameters configurable through mode register settings. The system can adjust detection thresholds, alert behaviors, and mitigation strategies to adapt to different RH attack types and scenarios. This configurability enhances versatility while maintaining reliability across various attack vectors that may not be covered by fixed DDR5 mitigation measures.
Data Source
AI summary
Methods and apparatus for row hammer (RH) mitigation and recovery. A host comprising a memory controller is configured to interface with one or more DRAM devices, such as DRAM DIMMs. The memory controller includes host-side RH mitigation logic and the DRAM devices include DRAM-side RH mitigation logic that cooperates with the host-side RH mitigation logic to perform RH mitigation and/or recovery operations in response to detection of RH attacks. The memory controller and DRAM device are configured to support an RH polling mode under which the memory controller periodically polls for RH attack detection indicia on the DRAM device that is toggled when the DRAM device detects an RH attack. The memory controller and DRAM device may also be configured to support an RH ALERT_n mode under which the use of an ALERT_n signal and pin is used to provide an alert to the memory controller to initiate RH mitigation and/or recovery.