3D MTJ Memory Cell Structure for High-Capacity Low-Power Storage
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Solution Overview
Problem
Existing memory devices face challenges in achieving high storage capacity with low power consumption, particularly in applications like cache memory and main memory, where fast access times and reduced power consumption are required.
Innovation Solution
A memory device structure is proposed with layers including a circuit and memory cells, utilizing transistors with metal oxide in the channel formation region and incorporating a conductor that causes the spin Hall effect, along with MTJ elements featuring a free layer connected to transistors, to enhance performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are stacked to increase storage capacity per unit area, then storage capacity is improved, but access time and power consumption are not optimized
Solution Approach 1:
The patent changes the material composition parameter of the transistor channel from conventional silicon to metal oxide, which fundamentally alters the electrical characteristics. This enables the memory device to achieve both high storage capacity through 3D stacking and low power consumption through the unique properties of metal oxide transistors, resolving the contradiction between capacity and energy efficiency
Solution Approach 2:
The patent employs composite material structures, specifically metal oxide in the transistor channel region combined with conventional MTJ memory elements. This composite approach allows the device to leverage the high-density storage capability of MTJ while using metal oxide transistors to reduce power consumption, achieving both goals simultaneously
2Ease of manufacture
If conventional transistors are used in memory cells, then manufacturing is easier, but power consumption increases
Solution Approach 1:
The patent changes the material parameter of the transistor channel from silicon to metal oxide, which modifies the electrical properties to reduce leakage current and power consumption. This material substitution maintains compatibility with existing semiconductor manufacturing processes while achieving significant power savings
3Quantity of substance
If 3D stacking is used to increase storage capacity, then capacity per unit area is improved, but device complexity increases
Solution Approach 1:
The patent divides the memory device into distinct functional layers: a first layer containing circuit elements and a second layer containing memory cells with MTJ elements. This segmentation allows for modular design and fabrication, reducing the overall complexity of 3D stacking by treating each layer as an independent unit that can be manufactured and tested separately
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides a memory device with lower power consumption and high storage capacity, suitable for applications requiring fast access times.
Implementation Method 1
The conductor includes a metal material causing a spin Hall effect when current flows through the conductor
Data Source
AI summary
A memory device with high storage capacity and low power consumption is provided. The memory device includes a first layer and a second layer including the first layer. The first layer includes a circuit, and the second layer includes a first memory cell. The circuit includes a bit line driver circuit and/or a word line driver circuit which transmits(s) a signal to the first memory cell. The first memory cell includes a first transistor, a second transistor, a conductor, and an MTJ element. The MTJ element includes a free layer. The free layer is electrically connected to the conductor. The first terminal of the first transistor is electrically connected to a first terminal of the second transistor through the conductor. The free layer is positioned above the conductor. The circuit includes a transistor containing silicon in a channel formation region, and each of the first transistor and the second transistor contains a metal oxide in a channel formation region.