Ferroelectric Memory Cell Stack for Disturbance and RC Delay Control
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Solution Overview
Problem
Traditional ferroelectric materials face integration challenges with CMOS processes, leading to high bit-flipping issues and reduced access speed due to wide coercive field distribution and RC delay, which are not adequately addressed by existing anti-interference schemes.
Innovation Solution
A crossbar array ferroelectric capacitor memory with a stacked structure of a top electrode, capacitance-variable dielectric layer, intermediate metal layer, ferroelectric dielectric layer, and bottom electrode, utilizing a capacitance-variable selector to manage voltage distribution and reduce disturbances, achieving high-speed and high-density storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional ferroelectric materials (PZT, BTO) are used, then ferroelectric memory can achieve low power consumption and high speed, but they have low compatibility with CMOS processes and obvious size effect, making integration in advanced process nodes impossible
Solution Approach 1:
The patent changes the material parameter from traditional perovskite ferroelectric materials to hafnium oxide-based materials, which have different physical and chemical properties that enable better CMOS compatibility while maintaining ferroelectric characteristics. This material substitution resolves the contradiction between achieving ferroelectric memory performance and ensuring ease of manufacture through standard CMOS processes.
2Ease of manufacture
If HfO2-based ferroelectric materials are used, then CMOS compatibility and miniaturization are improved, but polycrystalline and multi-domain characteristics cause wide coercive field distribution, resulting in significant disturbances to unselected cells and serious bit-flipping problems
Solution Approach 1:
The patent introduces a resistive switching device as an intermediary component connected in series with the gate of the ferroelectric transistor. This intermediary device utilizes resistance differences at different voltages to increase RC delay at unselected cell gates, thereby reducing equivalent gate disturbance voltage and suppressing bit-flipping problems while maintaining the benefits of HfO2-based materials.
3Reliability
If resistive switching devices are connected in series with the gate of ferroelectric transistor, then RC delay at unselected cells is increased to reduce bit-flipping, but RC delay of selected cells also increases, reducing memory access speed
Solution Approach 1:
The patent applies local quality by making the resistive switching device's resistance state voltage-dependent: at low voltages (unselected cells), it presents high resistance to increase RC delay and reduce disturbance; at high voltages (selected cells), it transitions to low resistance to minimize RC delay and maintain fast access speed. This localized property variation resolves the contradiction between disturbance reduction and speed maintenance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed memory design reduces bit error rates and improves access speed by minimizing voltage disturbances and RC delay, enhancing the storage window and reducing the bit error rate.
Implementation Method 1
when the voltage is high enough, metal atoms migrate and form metal filaments in the capacitance-variable dielectric layer, reducing the equivalent spacing between the electrode plates and significantly increasing the capacitance value of the capacitance-variable selector
Implementation Method 2
Ferroelectric dielectric materials, due to their asymmetric lattice structure, overall exhibit spontaneous polarization charges that can be controlled by an electric field, and the polarization reversal speed depends on the lattice relaxation time
Implementation Method 3
the selected memory cell is subjected to a full-swing voltage (twice the half-select voltage), so that the capacitance-variable selector changes to a high capacitance state, so that most of the voltage drops on the ferroelectric capacitor of the memory cell
Data Source
AI summary
A high-speed and high-density ferroelectric memory, and a preparation method therefor and an application thereof, belonging to the field of semiconductor memories. In the memory, multiple memory cells are arranged in an array, and the two sides of the array of the memory cells are connected to substantially orthogonal word lines and bit lines, the memory cell of the present invention adopts a stacked structure of a top electrode, a capacitance-variable dielectric layer, an intermediate metal layer, a ferroelectric dielectric layer, and a bottom electrode, which is electrically equivalent to a ferroelectric capacitor and a capacitance-variable selector connected in series, by regulating the voltage division relationship of the memory cells, the voltage division of the ferroelectric capacitor in the unselected cells is reduced, so that its disturbance is reduced; and by using the capacitors in series, the RC delay of memory cells is decreased, so as to improve the memory access speed. Therefore, the disturbance of unselected cells is reduced, the storage window of the memory is improved, the bit error rate of the memory is reduced, and the memory access speed is improved, without increasing additional area overhead.