SOT-MRAM Unit Cell Layout for Lower Write Energy and Capacitance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor memory devices face challenges in achieving high integration density and low power consumption, particularly in magnetic memory devices, which are needed for next-generation applications.
Innovation Solution
The use of spin-orbit torque (SOT) materials in semiconductor memory devices, incorporating a spin-orbit torque pattern, magnetic tunnel junction pattern, and transistors, with optimized word and bit lines, dopant regions, and integrated cell layouts to enhance integration density and reduce write energy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional magnetic memory device layouts are used, then device functionality is maintained, but integration density is limited
Solution Approach 1:
The patent merges the read and write transistor gate electrodes into a shared structure where the read word line and write word line are positioned adjacently and share common dopant regions. This merging of control structures reduces the overall cell area while maintaining distinct read and write functionality, directly improving integration density without proportionally increasing device complexity
Solution Approach 2:
The shared dopant regions serve dual purposes: they function as source/drain regions for both the read transistor and write transistor. This multi-functional design eliminates the need for separate dedicated regions for each transistor type, reducing the total number of components needed per memory cell and thereby increasing integration density
2Use of energy by moving object
If conventional write mechanisms are used, then data storage is achieved, but write energy consumption is high
Solution Approach 1:
The patent introduces a spin-orbit torque (SOT) pattern as an intermediary mechanism between the write current and the magnetic tunnel junction. The write current flows through the SOT pattern (composed of heavy metal materials) which generates spin-orbit torque to switch the magnetization state, rather than directly switching the MTJ. This intermediary approach reduces the write energy requirement while maintaining reliable data storage through the spin Hall effect or Rashba effect
Solution Approach 2:
The patent changes the write mechanism from direct spin-transfer torque (STT) switching to spin-orbit torque (SOT) switching by modifying the current path and material composition. The write current is redirected to flow through the SOT pattern adjacent to the MTJ, utilizing spin-orbit coupling in heavy metal materials to achieve magnetization switching with lower energy consumption while preserving data storage reliability
3Speed
If bit line capacitance is not minimized, then circuit simplicity is maintained, but switching speed and reliability are reduced
Solution Approach 1:
The patent extracts the read transistor gate control from the bit line and places it on a dedicated read word line. This separation removes the capacitive loading of the bit line, allowing faster switching speeds for both read and write operations. The bit line is used solely for data transfer, while the read word line provides gate control, dividing functions to reduce bit line capacitance effects
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Improves integration density and reduces write energy consumption by utilizing SOT patterns and magnetic tunnel junctions, while also minimizing bit-line capacitance for faster and more reliable data storage.
Implementation Method 1
a spin-orbit torque (SOT) pattern having a first end connected to the source line and a second end opposite to the first end
Implementation Method 2
a magnetic tunnel junction pattern extending on the SOT pattern
Data Source
AI summary
A semiconductor memory device includes first and second word lines, a bit line, a source line, and a memory cell. The memory cell includes a spin-orbit torque (SOT) pattern having a first end electrically coupled to the source line, a magnetic tunnel junction pattern extending adjacent the SOT pattern, and a read transistor having a first current carrying terminal electrically coupled to a first end of the magnetic tunnel junction pattern, a second current carrying terminal electrically coupled to the bit line, and a gate terminal electrically coupled to the first word line. The memory cell also includes a write transistor having a first current carrying terminal electrically coupled to a second end of the SOT pattern, a second current carrying terminal electrically coupled to the first end of the magnetic tunnel junction pattern, and a gate terminal electrically coupled to the second word line.