Ferroelectric Vertical Memory Cell for Low-Voltage Dual-Mode Operation
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Solution Overview
Problem
Existing memory devices face challenges in achieving high integration and electrical reliability while supporting both volatile and non-volatile memory operations with improved programming and sensing operations at lower operating voltages.
Innovation Solution
A memory device design incorporating ferroelectric dielectric layers in its structure, allowing it to selectively operate as volatile or non-volatile memory, featuring a vertical channel layer and capacitor structures with ferroelectric materials to enhance integration and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional memory structures are used, then device complexity is reduced, but integration density and electrical reliability deteriorate
Solution Approach 1:
The patent transitions from planar memory structures to vertical channel structures, stacking multiple memory layers in the vertical dimension. This allows higher integration density while maintaining electrical reliability through the ferroelectric material's spontaneous polarization properties that persist without external power.
Solution Approach 2:
The patent employs composite material structures combining ferroelectric materials with conventional semiconductor materials. The ferroelectric layer is integrated within the memory cell structure, providing non-volatile storage capability while the conventional materials maintain compatibility with existing manufacturing processes and electrical characteristics.
2Adaptability or versatility
If ferroelectric materials are integrated into memory structures, then non-volatile memory operation and electrical reliability are improved, but device complexity increases
Solution Approach 1:
The ferroelectric dielectric layers serve multiple functions simultaneously: they act as gate dielectrics for voltage application, as storage media for non-volatile data retention through spontaneous polarization, and as part of the capacitor structure. This multi-functionality enables both volatile and non-volatile memory operations within the same device architecture.
Solution Approach 2:
The memory device is divided into multiple stacked layers, each with specific functions. The ferroelectric dielectric layers are segmented and positioned at different levels (first and second dielectric layers), allowing independent control and operation of different memory cells while simplifying the overall control logic through modular architecture.
3Use of energy by moving object
If operating voltage is reduced, then power consumption is lowered, but programming and sensing operation efficiency deteriorates
Solution Approach 1:
The patent exploits the ferroelectric material's spontaneous polarization parameter, which allows stable charge storage at lower voltage levels. The coercive field of the ferroelectric material enables reliable switching and retention of polarization states at reduced operating voltages, improving energy efficiency without sacrificing programming or sensing operation effectiveness.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design enables higher integration and electrical reliability, supporting both volatile and non-volatile memory operations with improved programming and sensing efficiency at reduced voltage levels.
Implementation Method 1
Ferroelectric materials that maintain spontaneous polarization by aligning internal electric dipole moments even in an absence of an external electric field are being studied.
Implementation Method 2
Ferroelectric materials that maintain spontaneous polarization by aligning internal electric dipole moments even in an absence of an external electric field
Data Source
AI summary
A memory device includes a bit line extending in a first horizontal direction, a vertical channel layer extending in a vertical direction on the bit line, a first dielectric layer and a second dielectric layer both extending in the vertical direction with the vertical channel layer therebetween, a pair of word lines facing each other with the vertical channel layer, the first dielectric layer, and the second dielectric layer therebetween, a plate line positioned on the vertical channel layer, the first dielectric layer, and the second dielectric layer, and a capacitor structure arranged on the plate line, and at least one of the first or second dielectric layers includes a ferroelectric.