3D Vertical Ferroelectric Memory for High-Density DRAM Replacement
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Solution Overview
Problem
Conventional DRAMs face challenges in achieving high-density and low-power consumption, necessitating the development of a three-dimensional vertical single-transistor ferroelectric memory to replace them, particularly for applications in artificial intelligence chips that require large numbers of instantaneous memory cells.
Innovation Solution
A three-dimensional vertical single-transistor ferroelectric memory is manufactured using a substrate with an insulating dielectric layer, a channel structure, and a gate stack structure that includes a ferroelectric insulating layer and gate electrode, where the channel material has high mobility and the ferroelectric material is HZO, HALO, or PZT, with a method that involves forming a channel structure through the insulating material layer and stacking isolation oxide, ferroelectric, and gate materials to achieve a 3D NAND-like structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional 1T1C DRAM structure is used, then manufacturing process is simple, but storage density is low and power consumption is high
Solution Approach 1:
The patent transitions from a planar 2D structure to a three-dimensional vertical structure. The channel structure extends vertically through the insulating dielectric layer, and the gate stack structure is positioned adjacent to the channel region in 3D space, enabling higher storage density by utilizing the third dimension for cell arrangement.
Solution Approach 2:
The gate stack structure is positioned within the insulating dielectric layer at a position adjacent to the channel region, with the gate electrode surrounding the channel structure. This nested arrangement allows the gate to control the channel from multiple sides, improving capacitive coupling efficiency and enabling higher density.
2Quantity of substance
If planar structure is used, then manufacturing is easier, but storage density cannot be increased further
Solution Approach 1:
The patent adopts a vertical three-dimensional structure where the channel structure runs through the insulating dielectric layer from the substrate upward. The gate stack structure is positioned adjacent to the channel region in the vertical dimension, allowing multiple memory cells to be stacked vertically, thereby increasing storage density without expanding the planar footprint.
Solution Approach 2:
The memory structure is segmented into distinct functional regions: the substrate, insulating dielectric layer, channel structure with source-drain and channel regions, and gate stack structure. This segmentation allows for modular manufacturing processes similar to 3D NAND, facilitating easier fabrication of high-density structures.
3Quantity of substance
If physical thickness is increased, then storage density improves, but capacitive coupling strength decreases
Solution Approach 1:
The gate electrode is positioned to surround the channel structure, with the ferroelectric insulating layer adjacent to the channel region. This nested configuration maximizes the overlap area between the gate and channel, strengthening capacitive coupling. The gate stack structure is disposed in the insulating dielectric layer at a position that ensures optimal electric field coupling between the gate electrode and channel, maintaining strong control over the channel current despite increased vertical thickness.
Solution Approach 2:
The gate stack structure comprises a ferroelectric insulating layer and a gate electrode, forming a composite structure that provides both strong capacitive coupling and non-volatile memory functionality. The ferroelectric material enables strong polarization control, enhancing the coupling efficiency between gate and channel.
4Use of energy by moving object
If conventional DRAM is used, then power consumption is high, but ferroelectric material adds manufacturing complexity
Solution Approach 1:
The gate stack structure integrates a ferroelectric insulating layer with a gate electrode, forming a composite structure that combines the benefits of DRAM (single transistor per cell) with the advantages of ferroelectric materials (non-volatility, low power consumption). The ferroelectric material's ability to retain polarization states without power enables non-volatile operation, reducing overall power consumption while maintaining manufacturability through established semiconductor processes.
Data Source
AI summary
Provided are a three-dimensional vertical single transistor ferroelectric memory and a manufacturing method thereof. The ferroelectric memory comprises: a substrate; an insulating dielectric layer provided at the substrate; a channel structure extending through the insulating dielectric layer and connected to the substrate, the channel structure having a source/drain region and a channel region connected to the source/drain region; and a gate stack structure arranged around the channel structure and provided in the insulating dielectric layer opposite to the channel region, the gate stack structure comprising a ferroelectric insulation layer and a gate sequentially stacked in a direction away from the channel structure. The ferroelectric memory having the above structure can replace conventional DRAMs. Therefore, the invention realizes a high intensity high speed memory.