3D Ferroelectric Memory Cell Layout Beyond Patterning Limits
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Solution Overview
Problem
The increasing degree of integration in semiconductor devices is limited by the resolution limits of pattern formation processes, making it difficult to achieve high performance and low cost, prompting the need for three-dimensional semiconductor devices with improved fine patterning capabilities.
Innovation Solution
A non-volatile memory device is developed with a ferroelectric memory cell structure that includes a ferroelectric layer, a channel layer, and conductive fillers extending vertically, connected to bit lines and common source lines, enhancing the efficiency of data storage and retrieval in a three-dimensional configuration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If planar or two-dimensional semiconductor devices are used, then manufacturing process is simpler, but degree of integration is limited by area occupied by unit cells
Solution Approach 1:
The patent transitions from two-dimensional planar structures to three-dimensional vertical structures by stacking multiple semiconductor layers (first semiconductor layer, second semiconductor layer, third semiconductor layer) with insulating layers between them. This vertical stacking enables higher degree of integration by utilizing the third dimension (depth) rather than only the two-dimensional plane, thereby increasing the number of memory cells per unit area without requiring more complex lateral patterning processes.
2Manufacturing precision
If design rules of semiconductor elements are rapidly decreased, then device density increases, but resolution limit of patterning process becomes a limiting factor
Solution Approach 1:
The invention addresses patterning resolution limits by moving from lateral miniaturization to vertical stacking. Instead of continuously reducing the lateral dimensions of semiconductor elements which is constrained by patterning resolution, the patent increases integration density by stacking multiple layers vertically. Each layer can be formed using existing patterning processes, avoiding the need for ultra-fine lateral patterning while achieving higher overall device density.
Solution Approach 2:
The patent divides the semiconductor device into multiple discrete layers (first semiconductor layer, second semiconductor layer, third semiconductor layer) separated by insulating layers. This segmentation allows each layer to be independently formed and patterned using standard processes, avoiding the need for a single complex ultra-fine patterning step. The vertical segmentation enables higher integration without pushing the lateral patterning resolution to its limits.
3Manufacturing precision
If three-dimensional semiconductor devices are implemented, then degree of integration is improved, but device structure becomes more complex
Solution Approach 1:
The patent employs a common source line structure that serves multiple functions: it acts as a source line for transistor channels, provides electrical connection to multiple memory cells, and serves as a reference potential. This multi-functionality reduces the number of separate components needed, simplifying the overall device structure while maintaining high degree of integration. The common source line approach avoids the need for individual source lines for each transistor, thereby reducing structural complexity.
Solution Approach 2:
The patent merges multiple functions into unified structures: the common source line conductive layer combines source line functionality with electrical interconnection, and the stacked semiconductor layers are integrated with shared insulating and conductive structures. By merging these functions rather than implementing them separately, the patent achieves high integration density without proportionally increasing structural complexity.
Data Source
AI summary
A non-volatile memory device includes a substrate; an insulating layer on the substrate; a bit line isolation layer on the insulating layer; a common source line conductive layer on the bit line isolation layer; a ferroelectric memory cell on the bit line isolation layer; a bit line connected to a top of the ferroelectric memory cell; and a common source line connected to the common source line conductive layer and electrically connected to the ferroelectric memory cell, wherein the ferroelectric memory cell includes a ferroelectric layer, a channel layer, a first conductive filler connected to the ferroelectric layer and the channel layer and extending in a vertical direction, and a second conductive filler connected to the ferroelectric layer and the channel layer and extending in the vertical direction, the first conductive filler is connected to the bit line, and the second conductive filler is connected to the common source line.