3D Ferroelectric Memory Pillars for Higher Storage Density
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Solution Overview
Problem
Existing semiconductor devices face challenges in increasing data storage capacity while maintaining efficient integration and interconnection, particularly in two-dimensional configurations.
Innovation Solution
A semiconductor device is designed with a three-dimensional structure incorporating ferroelectric layers that utilize polarization states for information storage, featuring vertical pillars and protrusion portions with conductive layers, enabling a ferroelectric tunnel junction memory element that enhances integration and electric field application.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a two-dimensional configuration is used for memory cells, then the device structure is simple and easy to manufacture, but the data storage capacity is limited
Solution Approach 1:
The patent transitions from a two-dimensional memory cell arrangement to a three-dimensional structure by introducing vertical pillars that extend through multiple interlayer insulating layers and horizontal electrodes. This vertical stacking enables multiple memory cells to be arranged in the vertical direction, significantly increasing data storage capacity while maintaining a compact footprint on the substrate.
Solution Approach 2:
The patent implements a nested structure where vertical pillars containing ferroelectric layers are embedded within holes formed through alternating interlayer insulating layers and horizontal electrodes. The vertical pillars are surrounded by multiple layers of insulating and conductive materials, creating a nested configuration that maximizes space utilization and storage density.
2Quantity of substance
If more memory cells are integrated in a given area, then data storage capacity increases, but interconnection complexity increases
Solution Approach 1:
The patent resolves interconnection complexity by utilizing the vertical dimension for signal routing. Horizontal electrodes are arranged at different vertical levels, allowing bit lines and word lines to be separated in the vertical direction. This three-dimensional interconnection scheme reduces the complexity of routing signals to and from densely packed memory cells compared to planar interconnection approaches.
3Quantity of substance
If ferroelectric layers are used for information storage, then data storage capacity and retention are improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent introduces interface insulating layers between the ferroelectric layers and adjacent conductive or insulating layers. These interface layers serve as mediators that protect the ferroelectric material from degradation caused by direct contact with electrodes or other materials, thereby improving device reliability and reducing the stringency of manufacturing precision requirements for the ferroelectric layer deposition.
4Reliability
If vertical pillars with ferroelectric layers are implemented, then memory window and electric field application are optimized, but device structure complexity increases
Solution Approach 1:
The patent divides the memory device into discrete vertical pillars, each containing segmented ferroelectric layers separated by interface insulating layers. This segmentation allows for independent formation and optimization of each memory cell unit, facilitating better control over electric field distribution and memory window characteristics while making the overall complex structure more manageable through modular design.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The three-dimensional structure improves data storage capacity and simplifies interconnection lines by utilizing ferroelectric tunnel junctions, increasing the memory window through optimized electric field application.
Implementation Method 1
a ferroelectric layer capable of storing information by utilizing a polarization state
Implementation Method 2
increasing the memory window through optimized electric field application
Data Source
AI summary
A semiconductor device includes: a substrate; stack structures including interlayer insulating layers and horizontal electrodes alternately stacked in a vertical direction on the substrate; a vertical pillar spaced apart from the substrate and provided in a hole penetrating through the stack structure; and protrusion portions provided between the vertical pillar and the horizontal electrodes, and spaced apart from each other in the vertical direction, and the vertical pillar includes: a conductive pillar in the hole; a first information storage layer covering a side surface and a bottom surface of the conductive pillar and including a ferroelectric layer; and an interface insulating layer covering an outer surface of the first information storage layer, and each of the protrusion portions includes a conductive layer disposed between the interface insulating layer and the horizontal electrodes.