Digital Storage TRIZ Cases

Vertical stacking with lateral recesses and sacrificial layers raises memory cell density while lowering parasitic capacitance in 3D memory fabrication.

Coupled ferromagnetic free layers in an MTJ cut MRAM write energy while preserving thermal stability through separate spin reversal.

Opposed fixed layers with different coercivity and spin polarization cut MTJ write current while protecting the tunneling layer.

A copper oxide and tungsten oxide bilayer boosts ion mobility and electron supply, enabling rapid lateral PMC electrodeposition.

Current-holding circuits and driving transistors enable low-power product-sum operation while reducing temperature and transistor variation effects.

By using adjacent bit lines as references, this DRAM sense amplifier removes edge reference arrays to cut chip area and support write-back.

Refresh-driven scrubbing and selective ECC correction cut DRAM bit errors while limiting extra operation time and power use.

A stacked NMOS-PMOS pair handles bidirectional write current in NVM bit cells, speeding programming while shrinking cell footprint.

A co-integrated FeRAM and OxRAM array shifts writes and reads to the better-suited memory, cutting energy use and improving endurance.

Hybrid copper bonding enables parallel read and write paths without serialization, cutting memory I/O latency, area, and power.

A FeFET memory array writes matrix data by column and reads by row to transpose data with less memory use and computational overhead.

A Ge-As-S-Se-group III chalcogenide composition suppresses phase separation, leakage current, and threshold voltage drift in memory switching layers.

Multiple non-volatile memory cells encode each synaptic weight, then analog currents are digitized and summed to improve accuracy while cutting area and power.

Local reference resistance compensation calibrates each sense amplifier to offset MRAM resistance variation and improve read margin.

A bilayer antiferroelectric tunneling junction uses ALD-built dielectric and antiferroelectric layers to raise on-state current and cut off-state leakage.

Alternating spin-orbit layer thickness and local pinning regions enable field-free domain wall motion with stable multi-resistance states.

Ferroelectric layers and charge-trap patterns enable denser 3D memory cells with faster erase operation and multiple data states.

Temperature-based sense-time offsets compensate threshold-voltage shifts in nonvolatile memory soft-bit reads for more reliable data retrieval.

Synchronized and opportunistic DRAM sub-channel refresh reduces traffic blocking, balances queues, and improves data bus efficiency.

Switchable wide and narrow memory access modes cut pin and trace demands, letting controllers support more modules with balanced latency and cost.

Direct redundant control switching bypasses decoding circuits to speed defective row replacement and reduce leakage in memory arrays.

An inclined non-magnetic pattern in an antiferromagnetically coupled magnetic track lowers domain wall injection current density and device stress.

A floating comparator with bias offset compensation removes input capacitors, speeding memory reads while cutting sensing power.

A fly bitline layout enables pseudo-triple-port SRAM to support simultaneous read/write while preserving bitcell density and BEOL routing efficiency.

Comparator-based ZQ calibration and temperature sensing keep NAND flash I/O impedance matched for more reliable, efficient data transmission.

XOR logic ties ECC bits to the current addressing mode, detecting unauthorized mode changes without extra memory or hardware.

A filtering circuit inside the memory device cuts CPU data transfers, reducing latency, power use, and memory-system bottlenecks.

Underground bit lines self-align to source and drain regions, cutting surface interconnect complexity, area use, and signal loss in memory arrays.

Separate write and read transistors let one node program multiple resistors, cutting operating voltage while increasing bit-per-cell capacity.

Prefetching bad column addresses cuts timing path delay in non-volatile memory redundancy circuits while preserving defect handling reliability.

Alternating opposite read-voltage polarities in ferroelectric memory cells prevents imprint degradation and preserves read reliability.

A vertically stacked complementary transistor pair speeds bidirectional NVM writes while shrinking bit cell footprint and power use.

Intermediate wordline boosting maintains voltage and timing over longer memory bank rows, increasing storage capacity and area use.

Vertical ferroelectric tunnel junction pillars raise storage density and simplify interconnects while widening the memory window.

Multi-layer word and bit line routing removes strap cells in dual-port memory arrays, saving area while maintaining signal connectivity.

A carbon barrier layer plus a high-melting conductive layer limits diffusion and preserves selector switching in resistive memory cells.

A dual-side I/O and bit-line twist layout reduces LDE-driven pass-gate threshold shifts, balancing WVmin in DP SRAM.

Shared drive lines and switching transistors cut gain-cell memory wiring and drivers while preserving independent, non-destructive read and write.

Separate local plate drivers apply different voltages to selected and unselected cells, reducing ferroelectric capacitor disturbance and power use.

Hardware glitch detectors and remote processing units confirm alarms to protect memory systems from repeated glitch attacks.

Separate frontside and backside bit lines in CFET SRAM cut parasitic loading to improve read/write speed and power without reducing cell density.

Selective metadata planes and virtual plane remapping enable single-pass data, metadata, and ECC access without sacrificing addressable memory space.

Adjacent-path waveform detection drives real-time FFE strength control to cut crosstalk jitter and phase delay in high-speed parallel links.

Selective column-plane remapping stores metadata and ECC in one pass, then reclaims that space for data when metadata is not needed.

Timed bit-line equalization and offset cancellation improve memory read accuracy when transistor driving strengths differ.

A three-layer nonmagnetic buffer stabilizes crystal structure and anti-ferromagnetic coupling in MRAM while limiting layer count and cost.

By stacking control circuitry above the memory array, this case cuts footprint while supporting faster switching and lower power.

Interface and defect-engineering layers control oxygen vacancies and filament size in RRAM, enabling high resistance with lower voltage and power.

Inclined horizontal and vertical channel portions increase memory integration density and current drive while helping preserve production yield.

A current-driven SOT-MRAM circuit uses reference current sources to overcome parasitic resistance and leakage, improving write uniformity and endurance.