Inclined Vertical Channel Memory Structure for Density and Yield

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Solution Overview

Problem

Existing semiconductor devices face challenges in maintaining production yield and improving integration density and resistance as design rules decrease, requiring new technologies for vertical channel transistors.

Innovation Solution

The semiconductor memory device incorporates vertical channel transistors with horizontal and vertical channel portions, inclined channel patterns, and gate insulating layers to enhance integration density and current driving characteristics.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of moving object

If design rules are decreased to increase integration density, then integration density and operation speed are improved, but production yield deteriorates

Engineering Contradiction:
Improveintegration densityVSAvoidproduction yield
Core Design Contradiction:
Area of moving objectVSReliability

Solution Approach 1:

The patent transitions from planar channel transistors to vertical channel transistors by extending the channel in the vertical direction (third direction perpendicular to the substrate plane). This dimensional change allows higher integration density without proportionally decreasing design rules, thereby maintaining production yield while achieving improved integration density and operation speed.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Area of moving object

If vertical channel transistors are used to increase integration density, then integration density and resistance characteristics are improved, but device complexity increases

Engineering Contradiction:
Improveintegration densityVSAvoidtransistor structure complexity
Core Design Contradiction:
Area of moving objectVSDevice complexity

Solution Approach 1:

The channel pattern is divided into distinct segments: a horizontal channel portion connected to the bit line and vertical channel portions extending upward. This segmentation allows the vertical channel transistor to achieve high integration density through the vertical component while the horizontal portion maintains simple planar connectivity, effectively managing device complexity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The channel pattern employs asymmetric geometry with one horizontal portion and multiple vertical portions arranged in specific configurations. This asymmetric design optimizes the electrical characteristics and integration density while providing flexibility in manufacturing processes, thereby controlling device complexity.

Inventive Principle:
Principle #4Asymmetry

3Power

If vertical channel portions are spaced apart in inclined directions, then current driving characteristics are improved, but manufacturing precision requirements increase

Engineering Contradiction:
Improvecurrent driving characteristicsVSAvoidchannel pattern alignment precision
Core Design Contradiction:
PowerVSManufacturing precision

Solution Approach 1:

The patent specifies that vertical channel portions are spaced apart in a third direction inclined to the first and second directions, with the horizontal channel portion having specific dimensional relationships (e.g., width in the first direction, length in the second direction). These parameter specifications optimize current driving characteristics while providing clear manufacturing guidelines to control alignment precision requirements.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS20260082546A1Semiconductor memory device
Publication Date: 2026.03.19 SAMSUNG ELECTRONICS CO LTD
  • US20260082546A1 patent drawing
  • US20260082546A1 patent drawing
  • US20260082546A1 patent drawing

AI summary

A semiconductor memory device includes a bit line extending in a first direction on a substrate, a word line extending in a second direction perpendicular to the first direction, and a channel pattern including a horizontal channel portion connected to the bit line and extending along an inclined direction, and a vertical channel portion extended from the horizontal channel portion, wherein a portion of the horizontal channel portion is disposed between a top surface of the bit line and a bottom surface of the word line, wherein the vertical channel portion has a first sidewall in parallel with the second direction, wherein the horizontal channel portion has a second sidewall in parallel with the second direction, and wherein the first sidewall of the vertical channel portion is spaced apart from the second sidewall of the horizontal channel portion in the inclined direction.