MFMFET Array With Asymmetric Gate Areas for Low-Voltage Memory
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Solution Overview
Problem
Ferroelectric memory devices face issues with high write voltage, reliability, and access interference during read and write operations, limiting their random-access capabilities and memory performance.
Innovation Solution
A metal ferroelectric metal field effect transistor (MFMFET) array with a specific gate electrode area ratio and operation method that reduces operating voltage and minimizes write disturb problems, enabling improved reliability and random access without interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a 2T-MFMFET array architecture is used, then the memory cell structure is simplified, but serious access interference occurs during read and write operations
Solution Approach 1:
The patent segments the bit line into two separate bit lines (BL0 and BL1) for each memory cell, rather than sharing a single bit line. This segmentation allows selective activation of specific bit lines during read/write operations, preventing interference with other memory cells in the same row or column. The two bit lines are controlled by different word line combinations, enabling precise addressing without cross-talk.
Solution Approach 2:
The patent applies local quality by making the gate electrode area ratios different for the two FETs in each memory cell (e.g., 1:2, 1:3, or 1:4 ratio). This creates asymmetric local properties that enable differential operation modes. During read operations, one FET is strongly on while the other is weakly on, allowing selective charge transfer to the floating gate without affecting other cells. This local asymmetry is key to eliminating access interference.
2Measurement precision
If conventional read schemes are used with floating gate charging, then the memory state can be read, but negative voltage is required on the word line and the process is complex
Solution Approach 1:
The patent inverts the conventional read approach by using the ferroelectric layer's polarization state to directly control charge transfer to the floating gate through the asymmetric FET structure, rather than using complex voltage sequences. The read operation simply applies positive voltage to the relevant word line and bit line, allowing charge to flow to the floating gate if the FET is in the on state, eliminating the need for negative voltage word lines.
Solution Approach 2:
The patent enables self-service read operations where the memory cell's own ferroelectric polarization state automatically determines the charge transfer to the floating gate. The asymmetric FET structure ensures that when the ferroelectric layer is in a specific polarization state, charge naturally flows to the floating gate without external control, making the read operation automatic and simple.
3Reliability
If high write voltage is applied to switch ferroelectric polarization, then the memory state can be written, but the operating voltage is too high and reliability decreases
Solution Approach 1:
The patent changes the electrical parameters of the FETs by using different gate electrode area ratios, which fundamentally alters the voltage requirements for switching. The FET with the larger gate area can be strongly turned on with moderate voltage, while the FET with the smaller gate area remains weakly on or off. This parameter change allows write operations at lower voltages (e.g., 1.8V or 3.3V) compared to conventional ferroelectric memory requiring high voltages.
Solution Approach 2:
The patent creates local quality differences in the FET gate electrodes with area ratios of 1:2, 1:3, or 1:4. This local asymmetry means that during write operations, voltage applied to the bit line and word lines creates strong channel formation in one FET while the other FET remains weakly conductive. This local property difference enables reliable polarization switching at reduced voltages, improving both reliability and energy efficiency.
4Productivity
If all memory cells on the same row/column are accessed simultaneously, then array operation is efficient, but write disturb problems occur affecting unselected cells
Solution Approach 1:
The patent segments the bit line access into two independent channels (BL0 and BL1) that can be selectively activated. During array operations, only the specific bit line segment corresponding to the selected memory cell is activated, while other bit line segments remain inactive. This segmentation prevents write disturb to unselected cells in the same row or column, as they are isolated by the inactive bit line segments. The segmentation works together with the asymmetric FET structure to enable both high-speed array operation and write protection.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively lowers write voltage, enhances memory reliability, and allows for random access without write disturb issues, improving overall memory performance.
Implementation Method 1
Ferroelectric (FE) materials are materials that have spontaneous polarization; that is, in the absence of an electric field, the positive/negative charge centers are separated in the unit cell structure to form an electric dipole material
Implementation Method 2
When the electric field exceeds the positive coercive field (+Ec) or is lower than the negative coercive field (−Ec), the direction of the electric dipole of the ferroelectric material can be changed. When the applied electric field is removed, there will still be residual polarization (Pr) in the ferroelectric material
Implementation Method 3
The first FET has a first gate electrode and a first area. The second FET has a second gate electrode and a second area, and the first area and the second area have a ratio therebetween ranging from 1:50 to 1:2
Data Source
AI summary
A metallic ferroelectric metal (MFM) field effect transistor (FET) is provided that includes an MFM, a first FET and a second FET. The MFM has a first electrode. The first FET is electrically connected to the first electrode, and has a first gate electrode, wherein the first gate electrode has a first area. The second FET is electrically connected to the first electrode, and has a second gate electrode, wherein the second gate electrode has a second area, and the first area and the second area have a ratio therebetween ranging from 1:50 to 1:2.