DP SRAM Bit-Line Twist Layout for Consistent Write Voltage
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Layout dependent effects (LDE) in Dual-Port Static Random Access Memory (DP SRAM) devices lead to inconsistencies in electrical characteristics, such as increased threshold voltages of pass-gate transistors, resulting in higher minimum write voltage (WVmin) and compromising reliable operation.
Innovation Solution
Implementing a dual-side input/output (I/O) circuit and a twist structure for bit lines, where bit lines connect to short or long poly pass-gate transistors based on their proximity to the I/O, balancing WVmin and improving device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional single-side I/O circuit layout is used in DP SRAM, then manufacturing process is simpler, but LDE causes inconsistent electrical characteristics and higher WVmin
Solution Approach 1:
The I/O circuits are segmented into two separate groups: first I/O circuits positioned adjacent to the first memory array, and second I/O circuits positioned adjacent to the second memory array. This segmentation allows each I/O group to be optimized independently for its associated memory array, reducing LDE-induced variations in electrical characteristics and achieving consistent WVmin across both ports.
Solution Approach 2:
The patent employs asymmetric placement of I/O circuits relative to different memory arrays. By positioning first I/O circuits adjacent to the first memory array and second I/O circuits adjacent to the second memory array, the design creates an asymmetric layout that compensates for LDE effects, ensuring that both ports experience similar electrical characteristics despite their different physical locations.
2Manufacturing precision
If bit lines are connected uniformly to all memory cells, then routing is simpler, but LDE increases threshold voltage variations in pass-gate transistors
Solution Approach 1:
The bit line connection structure implements local quality by differentiating connection lengths based on memory cell location. Pass-gate transistors in the first memory array connect to bit lines through first-length connections, while pass-gate transistors in the second memory array connect through second-length connections. This localized differentiation compensates for LDE effects, ensuring consistent threshold voltages across all memory cells despite their varying distances from I/O circuits.
Data Source
AI summary
A memory circuit includes a first array including first memory cells, a second array located next to the first array along a first direction and including second memory cells, a first input/output located opposite the first array from the second array along the first direction, a second input/output located opposite the second array from the first array along the first direction, and a bit-line coupled to the first input/output, a transistor of a first one of the first memory cells, and a transistor of a first one of the second memory cells. The transistor of the first one of the first memory cells has a gate with a first length extending in a second direction perpendicular to the first direction, and the transistor of the first one of the second memory cells has a gate with a second length extending in the second direction and shorter than the second length.