Neuromorphic Synapse Array With Hybrid Analog-Digital Weight Summation
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Solution Overview
Problem
Existing neuromorphic systems face challenges in achieving precise and repeatable resistance changes in synaptic elements, leading to inaccuracies in learning and memory functions, and are hindered by high power consumption and large apparatus sizes due to the use of single memory cells as synaptic units.
Innovation Solution
A neuromorphic system utilizing a plurality of non-volatile memory cells as synaptic units, where the output signals are digitized and calculated to represent synaptic weights through a hybrid analog-digital computing method, reducing the number of memory cells required and enabling linear, predictable resistance changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a single memory cell is used as a synaptic unit to achieve precise resistance changes, then the learning and memory functions can be improved, but the apparatus size and power consumption increase significantly
Solution Approach 1:
The patent divides a single synaptic unit into multiple memory cells (e.g., 4 memory cells per synapse). Each memory cell stores a portion of the synaptic weight information, and their combined conductance represents the total synaptic weight. This segmentation allows precise resistance control through digital summation while reducing the area per synaptic unit compared to using a single large memory cell.
2Area of stationary object
If multiple memory cells are used as synaptic units to reduce apparatus size, then the system area decreases, but the resistance change control and repeatability become insufficient
Solution Approach 1:
The patent implements a feedback mechanism where the controller reads the conductance values of individual memory cells within a synaptic unit, calculates the total conductance, and adjusts individual cell states to achieve the target synaptic weight. This feedback loop ensures precise and repeatable resistance changes even when multiple memory cells are used, compensating for manufacturing variations and cell-to-cell variability.
Solution Approach 2:
The patent replaces the analog resistance control mechanism with a digital control approach. Instead of relying on continuous analog resistance adjustment in a single memory cell, the system uses digital selection and summation of discrete memory cell conductance values. This digital approach improves repeatability and control precision while enabling scalable integration.
3Device complexity
If analog computing method is used to maintain simple system structure, then the device complexity is low, but the power consumption increases
Solution Approach 1:
The patent employs periodic action by separating the computing operation into distinct phases: analog current summation for computation, followed by digital conversion and processing. The system performs analog multiply-accumulate operations during specific time windows, then converts results to digital domain for further processing. This time-multiplexed approach allows the system to benefit from low-power analog computing only when needed, while using power-efficient digital processing for control and data manipulation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for high-accuracy, smaller-sized, and low-power neuromorphic systems by expressing synaptic weights through a combination of memory cells, reducing the number of cells needed and minimizing system area and power consumption.
Implementation Method 1
a plurality of non-volatile memory cells capable of selectively storing a logical state, the non-volatile memory cells being arranged in a memory array... each synapse unit including a plurality of memory cells... capable of making a current to flow according to a set weight
Data Source
AI summary
A neuromorphic system according to an embodiment of the invention includes an input signal section that generates an input signal, a synapse section that includes a plurality of synaptic units that receive the input signal and makes a current to flow according to a set weight, each of the plurality of synaptic units including a plurality of non-volatile memory cells capable of selectively storing a logical state, the non-volatile memory cells being arranged in a memory array that include input electrode lines and output electrode lines crossing each other, and generates an output signal for each output electrode line by the input signal, a digital calculation section that digitizes the output signal generated for each output electrode line and calculates a sum of the digitized output signals, and a controller section that controls the input signal section, the synapse section, and the digital calculation section, and the controller section designates the number of digitized digits for each output electrode line and stores the logic state in the plurality of non-volatile memory cells according to a predetermined weight in each of the plurality of synaptic units, causes the input signal generated by the input signal section to be applied to each of a plurality of non-volatile memory cells of each of the plurality of synaptic units through the input electrode lines, generates, as the output signal, a sum of currents flowing from the plurality of non-volatile memory cells of each of the plurality of synaptic units by the applied input signal for each output electrode line, and causes the digital calculation section to digitize the output signal generated for each output electrode line according to the number of digits and calculate the sum of the digitized output signals.